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[Qemu-devel] [PATCH v4 0/4] sd: sdhci: correct transfer mode register us
From: |
P J P |
Subject: |
[Qemu-devel] [PATCH v4 0/4] sd: sdhci: correct transfer mode register usage |
Date: |
Wed, 15 Feb 2017 00:22:21 +0530 |
From: Prasad J Pandit <address@hidden>
Hello,
In SDHCI protocol, the 'Block Count Enable' bit of the Transfer Mode
register is used to control 's->blkcnt' value. This bit is not relevant
in single block transfers. Also, Transfer Mode register value could be
set such that 's->blkcnt' would not see an update during multi block
transfers. Thus leading to an infinite loop.
This patch set attempts to correct 'Block Count Enable' bit usage.
This series incorporates changes suggested in patch set v3:
-> https://lists.gnu.org/archive/html/qemu-devel/2017-02/msg02376.html
-> https://lists.gnu.org/archive/html/qemu-devel/2017-02/msg02905.html
Thank you.
--
Prasad J Pandit (4):
sd: sdhci: mask transfer mode register value
sd: sdhci: check transfer mode register in multi block transfer
sd: sdhci: conditionally invoke multi block transfer
sd: sdhci: Remove block count enable check in single block transfers
hw/sd/sdhci.c | 25 +++++++++++++------------
1 file changed, 13 insertions(+), 12 deletions(-)
--
2.9.3
- [Qemu-devel] [PATCH v4 0/4] sd: sdhci: correct transfer mode register usage,
P J P <=
[Qemu-devel] [PATCH v4 3/4] sd: sdhci: conditionally invoke multi block transfer, P J P, 2017/02/14
[Qemu-devel] [PATCH v4 4/4] sd: sdhci: Remove block count enable check in single block transfers, P J P, 2017/02/14