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[Qemu-devel] [PATCH v4 13/15] target/ppc: update OV/OV32 flags for add/s
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-devel] [PATCH v4 13/15] target/ppc: update OV/OV32 flags for add/sub |
Date: |
Fri, 24 Feb 2017 01:26:38 +0530 |
* SO and OV reflects overflow of the 64-bit result in 64-bit mode and
overflow of the low-order 32-bit result in 32-bit mode
* OV32 reflects overflow of the low-order 32-bit independent of the mode
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target/ppc/translate.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index f7d37b0..dc75cca 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -874,6 +874,7 @@ static inline void gen_op_arith_compute_ov(DisasContext
*ctx, TCGv arg0,
{
TCGv t0 = tcg_temp_new();
TCGv ov = tcg_temp_new();
+ TCGv ov32 = tcg_temp_new();
tcg_gen_xor_tl(ov, arg0, arg2);
tcg_gen_xor_tl(t0, arg1, arg2);
@@ -884,11 +885,19 @@ static inline void gen_op_arith_compute_ov(DisasContext
*ctx, TCGv arg0,
}
tcg_temp_free(t0);
if (NARROW_MODE(ctx)) {
- tcg_gen_ext32s_tl(ov, ov);
+ tcg_gen_extract_tl(ov, ov, 31, 1);
+ if (is_isa300(ctx)) {
+ tcg_gen_mov_tl(ov32, ov);
+ }
+ } else {
+ if (is_isa300(ctx)) {
+ tcg_gen_extract_tl(ov32, ov, 31, 1);
+ }
+ tcg_gen_extract_tl(ov, ov, 63, 1);
}
- tcg_gen_shri_tl(ov, ov, TARGET_LONG_BITS - 1);
- gen_op_update_ov_legacy(ov);
+ gen_op_update_ov(ctx, ov, ov32);
tcg_temp_free(ov);
+ tcg_temp_free(ov32);
}
static inline void gen_op_arith_compute_ca32(DisasContext *ctx, TCGv ca32,
--
2.7.4
- [Qemu-devel] [PATCH v4 00/15] POWER9 TCG enablements - part15, Nikunj A Dadhania, 2017/02/23
- [Qemu-devel] [PATCH v4 02/15] target/ppc: update ov flag from remaining paths, Nikunj A Dadhania, 2017/02/23
- [Qemu-devel] [PATCH v4 03/15] target/ppc: introduce helper_update_ca_legacy, Nikunj A Dadhania, 2017/02/23
- [Qemu-devel] [PATCH v4 12/15] target/ppc: update OV/OV32 for divide operations, Nikunj A Dadhania, 2017/02/23
- [Qemu-devel] [PATCH v4 01/15] target/ppc: introduce helper_update_ov_legacy, Nikunj A Dadhania, 2017/02/23
- [Qemu-devel] [PATCH v4 11/15] target/ppc: update OV/OV32 for mull[d, w] insns, Nikunj A Dadhania, 2017/02/23
- [Qemu-devel] [PATCH v4 08/15] target/ppc: update ca32 in arithmetic add, Nikunj A Dadhania, 2017/02/23
- [Qemu-devel] [PATCH v4 07/15] target/ppc: support for 32-bit carry and overflow, Nikunj A Dadhania, 2017/02/23
- [Qemu-devel] [PATCH v4 13/15] target/ppc: update OV/OV32 flags for add/sub,
Nikunj A Dadhania <=
- [Qemu-devel] [PATCH v4 04/15] target/ppc: add gen_op_update_ca_legacy() helper, Nikunj A Dadhania, 2017/02/23
- [Qemu-devel] [PATCH v4 06/15] target/ppc: remove xer split-out flags(so, ov, ca), Nikunj A Dadhania, 2017/02/23
- Re: [Qemu-devel] [PATCH v4 06/15] target/ppc: remove xer split-out flags(so, ov, ca), Richard Henderson, 2017/02/23
- Re: [Qemu-devel] [PATCH v4 06/15] target/ppc: remove xer split-out flags(so, ov, ca), Nikunj A Dadhania, 2017/02/23
- Re: [Qemu-devel] [PATCH v4 06/15] target/ppc: remove xer split-out flags(so, ov, ca), David Gibson, 2017/02/23
- Re: [Qemu-devel] [PATCH v4 06/15] target/ppc: remove xer split-out flags(so, ov, ca), Richard Henderson, 2017/02/24
- Re: [Qemu-devel] [PATCH v4 06/15] target/ppc: remove xer split-out flags(so, ov, ca), Nikunj A Dadhania, 2017/02/24
- Re: [Qemu-devel] [Qemu-ppc] [PATCH v4 06/15] target/ppc: remove xer split-out flags(so, ov, ca), Nikunj A Dadhania, 2017/02/24
- Re: [Qemu-devel] [PATCH v4 06/15] target/ppc: remove xer split-out flags(so, ov, ca), Richard Henderson, 2017/02/24
[Qemu-devel] [PATCH v4 05/15] target/ppc: add gen_op_update_ov_legacy() helper, Nikunj A Dadhania, 2017/02/23