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[Qemu-devel] [PATCH v5 0/8] POWER9 TCG enablements - part15

From: Nikunj A Dadhania
Subject: [Qemu-devel] [PATCH v5 0/8] POWER9 TCG enablements - part15
Date: Fri, 24 Feb 2017 11:16:36 +0530

This series contains implentation of CA32 and OV32 bits added to the 
ISA 3.0. Various fixed-point arithmetic instructions are updated to take
care of the newer flags. 

Finally the last patch adds new instruction mcrxrx, that helps reading 
the carry (CA and CA32) and the overflow (OV and OV32) flags

* Get back to the v3 implementation. Dropped removal of split 
  out variables.
* Remove checking of isa300 on the write side. Read side will do 
  the checking.

* Get rid of cpu_ca, cpu_ov, cpu_so split out variables
* As most of the patches under went changes, dropped the 
  reviewed-bys(except neg[.] patch)

* Add missing condition in narrow mode(add/subf), multiply and divide
* Drop nego patch, subf implementation is sufficient for setting OV and OV32
* Retaining neg[.], as the code is simplified.
* Fix OV resetting in compute_ov()

* Use these ISA 3.0 flag to enable CA32 and OV32
* Re-write ca32 compute routine
* Add setting of flags for "neg." and "nego."

Nikunj A Dadhania (8):
  target/ppc: support for 32-bit carry and overflow
  target/ppc: update ca32 in arithmetic add
  target/ppc: update ca32 in arithmetic substract
  target/ppc: update overflow flags for add/sub
  target/ppc: use tcg ops for neg instruction
  target/ppc: add ov32 flag for multiply low insns
  target/ppc: add ov32 flag in divide operations
  target/ppc: add mcrxrx instruction

 target/ppc/cpu.c            |  13 +++++-
 target/ppc/cpu.h            |   7 +++
 target/ppc/int_helper.c     |  53 +++++++++-------------
 target/ppc/translate.c      | 106 ++++++++++++++++++++++++++++++++++++++++----
 target/ppc/translate_init.c |   2 +-
 5 files changed, 138 insertions(+), 43 deletions(-)


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