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[Qemu-devel] [PULL 04/30] sd: sdhci: check transfer mode register in mul
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 04/30] sd: sdhci: check transfer mode register in multi block transfer |
Date: |
Mon, 27 Feb 2017 18:04:33 +0000 |
From: Prasad J Pandit <address@hidden>
In the SDHCI protocol, the transfer mode register value
is used during multi block transfer to check if block count
register is enabled and should be updated. Transfer mode
register could be set such that, block count register would
not be updated, thus leading to an infinite loop. Add check
to avoid it.
Reported-by: Wjjzhang <address@hidden>
Reported-by: Jiang Xin <address@hidden>
Signed-off-by: Prasad J Pandit <address@hidden>
Message-id: address@hidden
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/sd/sdhci.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index a65c77d..5adeab6 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -487,6 +487,11 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
uint32_t boundary_chk = 1 << (((s->blksize & 0xf000) >> 12) + 12);
uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk);
+ if (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || !s->blkcnt) {
+ qemu_log_mask(LOG_UNIMP, "infinite transfer is not supported\n");
+ return;
+ }
+
/* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for
* possible stop at page boundary if initial address is not page aligned,
* allow them to work properly */
@@ -798,11 +803,6 @@ static void sdhci_data_transfer(void *opaque)
if (s->trnmod & SDHC_TRNS_DMA) {
switch (SDHC_DMA_TYPE(s->hostctl)) {
case SDHC_CTRL_SDMA:
- if ((s->trnmod & SDHC_TRNS_MULTI) &&
- (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || s->blkcnt == 0)) {
- break;
- }
-
if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) {
sdhci_sdma_transfer_single_block(s);
} else {
--
2.7.4
- [Qemu-devel] [PULL 23/30] armv7m: Raise correct kind of UsageFault for attempts to execute ARM code, (continued)
- [Qemu-devel] [PULL 23/30] armv7m: Raise correct kind of UsageFault for attempts to execute ARM code, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 07/30] hw/arm/virt: fix cpu object reference leak, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 25/30] bcm2835_sdhost: add bcm2835 sdhost controller, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 05/30] sd: sdhci: conditionally invoke multi block transfer, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 30/30] hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 02/30] bcm2835_rng: Use qcrypto_random_bytes() rather than rand(), Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 06/30] sd: sdhci: Remove block count enable check in single block transfers, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 13/30] armv7m: Implement reading and writing of PRIGROUP, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 11/30] ARM i.MX timers: fix reset handling, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 27/30] bcm2835_gpio: add bcm2835 gpio controller, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 04/30] sd: sdhci: check transfer mode register in multi block transfer,
Peter Maydell <=
- [Qemu-devel] [PULL 03/30] sd: sdhci: mask transfer mode register value, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 29/30] hw/arm/exynos: Fix Linux kernel division by zero for PLLs, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 09/30] cputlb: Don't assume do_unassigned_access() never returns, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 14/30] armv7m: Rewrite NVIC to not use any GIC code, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 28/30] bcm2835: add sdhost and gpio controllers, Peter Maydell, 2017/02/27
- [Qemu-devel] [PULL 12/30] armv7m: Rename nvic_state to NVICState, Peter Maydell, 2017/02/27
- Re: [Qemu-devel] [PULL 00/30] target-arm queue, no-reply, 2017/02/27
- Re: [Qemu-devel] [PULL 00/30] target-arm queue, Peter Maydell, 2017/02/28