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[Qemu-devel] [PATCH v4 7/9] ppc/pnv: extend the machine with a XICSFabri
From: |
Cédric Le Goater |
Subject: |
[Qemu-devel] [PATCH v4 7/9] ppc/pnv: extend the machine with a XICSFabric interface |
Date: |
Wed, 29 Mar 2017 15:53:29 +0200 |
A XICSFabric QOM interface is used by the XICS layer to manipulate the
ICP and ICS objects. Let's define the associated handlers for the
PowerNV machine. All handlers should be defined even if there is no
ICS under the PowerNV machine yet.
Signed-off-by: Cédric Le Goater <address@hidden>
---
hw/ppc/pnv.c | 42 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 9505ca7dc09a..57560b09e04e 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -34,6 +34,7 @@
#include "qemu/cutils.h"
#include "qapi/visitor.h"
+#include "hw/ppc/xics.h"
#include "hw/ppc/pnv_xscom.h"
#include "hw/isa/isa.h"
@@ -739,6 +740,39 @@ static const TypeInfo pnv_chip_info = {
.abstract = true,
};
+/* The XICS layer needs valid handlers for the ICS objects also */
+static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
+{
+ return NULL;
+}
+
+static void pnv_ics_resend(XICSFabric *xi)
+{
+}
+
+static PowerPCCPU *ppc_get_vcpu_by_pir(int pir)
+{
+ CPUState *cs;
+
+ CPU_FOREACH(cs) {
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
+
+ if (env->spr_cb[SPR_PIR].default_value == pir) {
+ return cpu;
+ }
+ }
+
+ return NULL;
+}
+
+static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
+{
+ PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
+
+ return cpu ? ICP(cpu->intc) : NULL;
+}
+
static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
@@ -789,6 +823,7 @@ static void powernv_machine_class_props_init(ObjectClass
*oc)
static void powernv_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
+ XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
mc->desc = "IBM PowerNV (Non-Virtualized)";
mc->init = ppc_powernv_init;
@@ -799,6 +834,9 @@ static void powernv_machine_class_init(ObjectClass *oc,
void *data)
mc->no_parallel = 1;
mc->default_boot_order = NULL;
mc->default_ram_size = 1 * G_BYTE;
+ xic->icp_get = pnv_icp_get;
+ xic->ics_get = pnv_ics_get;
+ xic->ics_resend = pnv_ics_resend;
powernv_machine_class_props_init(oc);
}
@@ -809,6 +847,10 @@ static const TypeInfo powernv_machine_info = {
.instance_size = sizeof(PnvMachineState),
.instance_init = powernv_machine_initfn,
.class_init = powernv_machine_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_XICS_FABRIC },
+ { },
+ },
};
static void powernv_machine_register_types(void)
--
2.7.4
- [Qemu-devel] [PATCH v4 0/9] ppc/pnv: interrupt controller (POWER8), Cédric Le Goater, 2017/03/29
- [Qemu-devel] [PATCH v4 1/9] ppc/xics: introduce an 'intc' backlink under PowerPCCPU, Cédric Le Goater, 2017/03/29
- [Qemu-devel] [PATCH v4 2/9] spapr: move the IRQ server number mapping under the machine, Cédric Le Goater, 2017/03/29
- [Qemu-devel] [PATCH v4 3/9] ppc/xics: add a realize() handler to ICPStateClass, Cédric Le Goater, 2017/03/29
- [Qemu-devel] [PATCH v4 4/9] ppc/pnv: add a PnvICPState object, Cédric Le Goater, 2017/03/29
- [Qemu-devel] [PATCH v4 5/9] ppc/pnv: create the ICP object under PnvCore, Cédric Le Goater, 2017/03/29
- [Qemu-devel] [PATCH v4 6/9] ppc/pnv: add a helper to calculate MMIO addresses registers, Cédric Le Goater, 2017/03/29
- [Qemu-devel] [PATCH v4 7/9] ppc/pnv: extend the machine with a XICSFabric interface,
Cédric Le Goater <=
- [Qemu-devel] [PATCH v4 8/9] ppc/pnv: extend the machine with a InterruptStatsProvider interface, Cédric Le Goater, 2017/03/29
- [Qemu-devel] [PATCH v4 9/9] ppc/pnv: add memory regions for the ICP registers, Cédric Le Goater, 2017/03/29