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[Qemu-devel] [PATCH v5 1/9] spapr: move the IRQ server number mapping un
From: |
Cédric Le Goater |
Subject: |
[Qemu-devel] [PATCH v5 1/9] spapr: move the IRQ server number mapping under the machine |
Date: |
Mon, 3 Apr 2017 09:45:57 +0200 |
This is the second step to abstract the IRQ 'server' number of the
XICS layer. Now that the prereq cleanups have been done in the
previous patch, we can move down the 'cpu_dt_id' to 'cpu_index'
mapping in the sPAPR machine handler.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
---
hw/intc/xics_spapr.c | 5 ++---
hw/ppc/spapr.c | 3 ++-
hw/ppc/spapr_cpu_core.c | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c
index 58f100d379cb..f05308b897f2 100644
--- a/hw/intc/xics_spapr.c
+++ b/hw/intc/xics_spapr.c
@@ -52,9 +52,8 @@ static target_ulong h_cppr(PowerPCCPU *cpu, sPAPRMachineState
*spapr,
static target_ulong h_ipi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
target_ulong opcode, target_ulong *args)
{
- target_ulong server = xics_get_cpu_index_by_dt_id(args[0]);
target_ulong mfrr = args[1];
- ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), server);
+ ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]);
if (!icp) {
return H_PARAMETER;
@@ -122,7 +121,7 @@ static void rtas_set_xive(PowerPCCPU *cpu,
sPAPRMachineState *spapr,
}
nr = rtas_ld(args, 0);
- server = xics_get_cpu_index_by_dt_id(rtas_ld(args, 1));
+ server = rtas_ld(args, 1);
priority = rtas_ld(args, 2);
if (!ics_valid_irq(ics, nr) || !xics_icp_get(XICS_FABRIC(spapr), server)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 44c26e4be86c..3358dc9ba638 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -3024,9 +3024,10 @@ static void spapr_ics_resend(XICSFabric *dev)
ics_resend(spapr->ics);
}
-static ICPState *spapr_icp_get(XICSFabric *xi, int server)
+static ICPState *spapr_icp_get(XICSFabric *xi, int cpu_dt_id)
{
sPAPRMachineState *spapr = SPAPR_MACHINE(xi);
+ int server = xics_get_cpu_index_by_dt_id(cpu_dt_id);
return (server < spapr->nr_servers) ? &spapr->icps[server] : NULL;
}
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index 7db61bd72476..4e1a99591d19 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -64,7 +64,7 @@ static void spapr_cpu_init(sPAPRMachineState *spapr,
PowerPCCPU *cpu,
{
CPUPPCState *env = &cpu->env;
XICSFabric *xi = XICS_FABRIC(spapr);
- ICPState *icp = xics_icp_get(xi, CPU(cpu)->cpu_index);
+ ICPState *icp = xics_icp_get(xi, cpu->cpu_dt_id);
/* Set time-base frequency to 512 MHz */
cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
--
2.7.4
- [Qemu-devel] [PATCH v5 0/9] ppc/pnv: interrupt controller (POWER8), Cédric Le Goater, 2017/04/03
- [Qemu-devel] [PATCH v5 1/9] spapr: move the IRQ server number mapping under the machine,
Cédric Le Goater <=
- [Qemu-devel] [PATCH v5 2/9] spapr: allocate the ICPState object from under sPAPRCPUCore, Cédric Le Goater, 2017/04/03
- [Qemu-devel] [PATCH v5 3/9] ppc/xics: add a realize() handler to ICPStateClass, Cédric Le Goater, 2017/04/03
- [Qemu-devel] [PATCH v5 5/9] ppc/pnv: extend the machine with a XICSFabric interface, Cédric Le Goater, 2017/04/03
- [Qemu-devel] [PATCH v5 4/9] ppc/pnv: add a PnvICPState object, Cédric Le Goater, 2017/04/03
- [Qemu-devel] [PATCH v5 6/9] ppc/pnv: extend the machine with a InterruptStatsProvider interface, Cédric Le Goater, 2017/04/03
- [Qemu-devel] [PATCH v5 7/9] ppc/pnv: create the ICP object under PnvCore, Cédric Le Goater, 2017/04/03
- [Qemu-devel] [PATCH v5 8/9] ppc/pnv: add a helper to calculate MMIO addresses registers, Cédric Le Goater, 2017/04/03
- [Qemu-devel] [PATCH v5 9/9] ppc/pnv: add memory regions for the ICP registers, Cédric Le Goater, 2017/04/03
- Re: [Qemu-devel] [PATCH v5 0/9] ppc/pnv: interrupt controller (POWER8), David Gibson, 2017/04/05