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[Qemu-devel] [PATCH v2 0/8] pnv: improvement of LPC support and IPMI sup

From: Cédric Le Goater
Subject: [Qemu-devel] [PATCH v2 0/8] pnv: improvement of LPC support and IPMI support
Date: Mon, 10 Apr 2017 15:56:50 +0200


The first patches improve the LPC support for the POWER8NVL (nvlink)
systems and for multichip systems. Next, we add IPMI support to the
machine which is required to power off and reboot a PowerNV system. To
make use of it, a BT device and an BMC simulator need to be defined on
the command line:

    -device ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10

To improve the sensor and FRU support, one can use the following
options for the simulator:


To test, grab a kernel and a rootfs image here :


The full patchset is available here :




Changes since v1:

 - moved the IRQ handler in pnv_lpc.c and introduced pnv_lpc_isa_irq_create()
 - only add the "primary" property on the LPC bus of chip 0
 - reworked the assignement of the ISA IO base in the 'reg' array
 - changed the type of the 'bmc' attribute of the machine

Benjamin Herrenschmidt (1):
  ppc/pnv: Add support for POWER8+ LPC Controller

Cédric Le Goater (7):
  ppc/pnv: enable only one LPC bus
  ppc/pnv: scan ISA bus to populate device tree
  ppc/pnv: populate device tree for RTC devices
  ppc/pnv: populate device tree for serial devices
  ppc/pnv: populate device tree for IPMI BT devices
  ppc/pnv: add initial IPMI sensors for the BMC simulator
  ppc/pnv: generate an OEM SEL event on shutdown

 hw/ppc/Makefile.objs     |   2 +-
 hw/ppc/pnv.c             | 212 ++++++++++++++++++++++++++++++++++++++---------
 hw/ppc/pnv_bmc.c         | 122 +++++++++++++++++++++++++++
 hw/ppc/pnv_lpc.c         | 120 ++++++++++++++++++++++++---
 include/hw/ppc/pnv.h     |  11 +++
 include/hw/ppc/pnv_lpc.h |  10 +++
 6 files changed, 425 insertions(+), 52 deletions(-)
 create mode 100644 hw/ppc/pnv_bmc.c


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