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Re: [Qemu-devel] [PATCH v1 3/5] cadence_gem: Only trigger interrupts if
Re: [Qemu-devel] [PATCH v1 3/5] cadence_gem: Only trigger interrupts if the status register is set
Tue, 11 Apr 2017 09:00:41 -0700
On Tue, Apr 11, 2017 at 2:05 AM, Peter Maydell <address@hidden> wrote:
> On 10 April 2017 at 23:23, Alistair Francis <address@hidden> wrote:
>> On Mon, Apr 10, 2017 at 5:44 AM, Peter Maydell <address@hidden> wrote:
>>> Also the comment says "raise or lower interrupt based on current
>>> status", but the code will only ever do qemu_set_irq(..., 1),
>>> never 0. Which is right?
>> This is a little confusing. The interrupts are lowered when the ISR is
>> read, so the assumption was that we never need to clear them in the
>> gem_update_int_status(). Although then if we perform a reset nothing
>> will clear the interrupts until the ISR is read from.
> On QEMU reset the other end will be reset anyway so it will
> update its idea of whether the irq is asserted (and calling
> qemu_set_irq in a reset function is generally not a good idea).
> If the device has guest-programmable reset of some kind you'd
> need to clear the irq lines then, though.
Ok, that explains why it was always working.
I still like the idea of all irq updates (raise or lower) being done
in a single function. Instead of how it was previously where the
raises where in one function and the lower was in the read function.
That way if in some future IP version the ISR is cleared somewhere
else the interrupt logic is ready to handle it.
I did make one small error in my V2 though, so I'll send a V3 with the
consolidation still in it.
> -- PMM
[Qemu-devel] [PATCH v1 2/5] cadence_gem: Correct the multi-queue can rx logic, Alistair Francis, 2017/04/04
[Qemu-devel] [PATCH v1 1/5] cadence_gem: Read the correct queue descriptor, Alistair Francis, 2017/04/04
- [Qemu-devel] [PATCH v1 5/5] xlnx-zynqmp: Set the Cadence GEM revision, (continued)