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Re: [Qemu-devel] [PATCH 4/7] target/openrisc: implement shadow registers

From: Richard Henderson
Subject: Re: [Qemu-devel] [PATCH 4/7] target/openrisc: implement shadow registers
Date: Tue, 18 Apr 2017 01:11:53 -0700
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0

On 04/16/2017 04:23 PM, Stafford Horne wrote:
Shadow registers are part of the openrisc spec along with sr[cid], as
part of the fast context switching feature.  When exceptions occur,
instead of having to save registers to the stack if enabled the CID will
increment and a new set of registers will be available.

This patch only implements shadow registers which can be used as extra
scratch registers via the mfspr and mtspr if required.  This is
implemented in a way where it would be easy to add on the fast context
switching, currently cid is hardcoded to 0.

I'm not especially keen on this half-conversion.
If CID cannot be changed, then

-    target_ulong gpr[32];     /* General registers */
+    target_ulong shadow_gpr[16][32]; /* Shadow registers */
+    target_ulong * gpr;       /* General registers (backed by shadow) */

this pointer should not be necessary.  Just use a union, or even just

    target_ulong gpr[32];
    target_ulong shadow_gpr[15][32];

for now.

Alternately, add accessor functions that take the whole ENV (which would be able to read CID, when needed). C.f.

    uint64_t cpu_alpha_load_gr(CPUAlphaState *env, unsigned reg);
    void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val);

If/when CID can be changed, then we can talk about various ways
that this can be modeled within TCG.


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