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[Qemu-devel] [PULL 22/24] arm: Track M profile handler mode state in TB
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 22/24] arm: Track M profile handler mode state in TB flags |
Date: |
Thu, 20 Apr 2017 17:41:08 +0100 |
For M profile exception-return handling we'd like to generate different
code for some instructions depending on whether we are in Handler
mode or Thread mode. This isn't the same as "are we privileged
or user", so we need an extra bit in the TB flags to distinguish.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
---
target/arm/cpu.h | 9 +++++++++
target/arm/translate.h | 1 +
target/arm/translate.c | 1 +
3 files changed, 11 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index ab86943..1055bfe 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2291,6 +2291,9 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState
*env)
#define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT)
#define ARM_TBFLAG_BE_DATA_SHIFT 20
#define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT)
+/* For M profile only, Handler (ie not Thread) mode */
+#define ARM_TBFLAG_HANDLER_SHIFT 21
+#define ARM_TBFLAG_HANDLER_MASK (1 << ARM_TBFLAG_HANDLER_SHIFT)
/* Bit usage when in AArch64 state */
#define ARM_TBFLAG_TBI0_SHIFT 0 /* TBI0 for EL0/1 or TBI for EL2/3 */
@@ -2327,6 +2330,8 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState
*env)
(((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT)
#define ARM_TBFLAG_BE_DATA(F) \
(((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT)
+#define ARM_TBFLAG_HANDLER(F) \
+ (((F) & ARM_TBFLAG_HANDLER_MASK) >> ARM_TBFLAG_HANDLER_SHIFT)
#define ARM_TBFLAG_TBI0(F) \
(((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT)
#define ARM_TBFLAG_TBI1(F) \
@@ -2517,6 +2522,10 @@ static inline void cpu_get_tb_cpu_state(CPUARMState
*env, target_ulong *pc,
}
*flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT;
+ if (env->v7m.exception != 0) {
+ *flags |= ARM_TBFLAG_HANDLER_MASK;
+ }
+
*cs_base = 0;
}
diff --git a/target/arm/translate.h b/target/arm/translate.h
index abb0760..3d0e8a6 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -31,6 +31,7 @@ typedef struct DisasContext {
bool vfp_enabled; /* FP enabled via FPSCR.EN */
int vec_len;
int vec_stride;
+ bool v7m_handler_mode;
/* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
* so that top level loop can generate correct syndrome information.
*/
diff --git a/target/arm/translate.c b/target/arm/translate.c
index f28c4ca..4fe7692 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -11780,6 +11780,7 @@ void gen_intermediate_code(CPUARMState *env,
TranslationBlock *tb)
dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
dc->c15_cpar = ARM_TBFLAG_XSCALE_CPAR(tb->flags);
+ dc->v7m_handler_mode = ARM_TBFLAG_HANDLER(tb->flags);
dc->cp_regs = cpu->cp_regs;
dc->features = env->features;
--
2.7.4
- [Qemu-devel] [PULL 20/24] arm: Move condition-failed codepath generation out of if(), (continued)
- [Qemu-devel] [PULL 20/24] arm: Move condition-failed codepath generation out of if(), Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 11/24] cadence_gem: Read the correct queue descriptor, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 09/24] arm/kvm: Remove trailing newlines from error_report(), Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 03/24] hw/char/exynos4210_uart: Constify static array and few arguments, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 08/24] stellaris: Don't hw_error() on bad register accesses, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 05/24] target/arm: Add missing entries to excnames[] for log strings, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 02/24] hw/arm/exynos: Convert fprintf to qemu_log_mask/error_report, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 01/24] hw/arm/boot: take Linux/arm64 TEXT_OFFSET header field into account, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 13/24] cadence_gem: Correct the interupt logic, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 21/24] arm: Abstract out "are we singlestepping" test to utility function, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 22/24] arm: Track M profile handler mode state in TB flags,
Peter Maydell <=
- [Qemu-devel] [PULL 24/24] arm: Remove workarounds for old M-profile exception return implementation, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 07/24] target/arm: Add assertion about FSC format for syndrome registers, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 10/24] hw/arm: Qomify pxa2xx.c, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 04/24] hw/misc/exynos4210_pmu: Reorder local variables for readability, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 23/24] arm: Implement M profile exception return properly, Peter Maydell, 2017/04/20
- [Qemu-devel] [PULL 06/24] arm: Move excnames[] array into arm_log_exceptions(), Peter Maydell, 2017/04/20
- Re: [Qemu-devel] [PULL 00/24] target-arm queue, Peter Maydell, 2017/04/20