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[Qemu-devel] [PULL 45/47] target/ppc: Flush TLB on write to PIDR
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 45/47] target/ppc: Flush TLB on write to PIDR |
Date: |
Mon, 24 Apr 2017 11:59:25 +1000 |
From: Suraj Jitindar Singh <address@hidden>
The PIDR (process id register) is used to store the id of the currently
running process, which is used to select the process table entry used to
perform address translation. This means that when we write to this register
all the translations in the TLB become outdated as they are for a
previously running process. Thus when this register is written to we need
to invalidate the TLB entries to ensure stale entries aren't used to
to perform translation for the new process, which would result in at best
segfaults or alternatively just random memory being accessed.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Reviewed-by: David Gibson <address@hidden>
[dwg: Fixed compile error for 32-bit targets]
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/helper.h | 1 +
target/ppc/misc_helper.c | 8 ++++++++
target/ppc/translate_init.c | 10 ++++++++--
3 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 6d77661..bb6a94a 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -709,6 +709,7 @@ DEF_HELPER_FLAGS_1(load_601_rtcu, TCG_CALL_NO_RWG, tl, env)
DEF_HELPER_FLAGS_1(load_purr, TCG_CALL_NO_RWG, tl, env)
#endif
DEF_HELPER_2(store_sdr1, void, env, tl)
+DEF_HELPER_2(store_pidr, void, env, tl)
DEF_HELPER_FLAGS_2(store_tbl, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(store_tbu, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(store_atbl, TCG_CALL_NO_RWG, void, env, tl)
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index fa573dd..0e42178 100644
--- a/target/ppc/misc_helper.c
+++ b/target/ppc/misc_helper.c
@@ -88,6 +88,14 @@ void helper_store_sdr1(CPUPPCState *env, target_ulong val)
}
}
+void helper_store_pidr(CPUPPCState *env, target_ulong val)
+{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
+
+ env->spr[SPR_BOOKS_PID] = val;
+ tlb_flush(CPU(cpu));
+}
+
void helper_store_hid0_601(CPUPPCState *env, target_ulong val)
{
target_ulong hid0;
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index aa0c44d..77e5463 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -394,8 +394,14 @@ static void spr_write_sdr1 (DisasContext *ctx, int sprn,
int gprn)
gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
}
-/* 64 bits PowerPC specific SPRs */
#if defined(TARGET_PPC64)
+/* 64 bits PowerPC specific SPRs */
+/* PIDR */
+static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
+}
+
static void spr_read_hior (DisasContext *ctx, int gprn, int sprn)
{
tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
@@ -8200,7 +8206,7 @@ static void gen_spr_power8_book4(CPUPPCState *env)
KVM_REG_PPC_ACOP, 0);
spr_register_kvm(env, SPR_BOOKS_PID, "PID",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_pidr,
KVM_REG_PPC_PID, 0);
spr_register_kvm(env, SPR_WORT, "WORT",
SPR_NOACCESS, SPR_NOACCESS,
--
2.9.3
- [Qemu-devel] [PULL 24/47] ppc/pnv: create the ICP object under PnvCore, (continued)
- [Qemu-devel] [PULL 24/47] ppc/pnv: create the ICP object under PnvCore, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 26/47] ppc/pnv: add memory regions for the ICP registers, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 46/47] e500, book3s: mfspr 259: Register mapped/aliased SPRG3 user read, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 28/47] ppc/pnv: Add OCC model stub with interrupt support, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 44/47] spapr-cpu-core: Release ICPState object during CPU unrealization, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 25/47] ppc/pnv: add a helper to calculate MMIO addresses registers, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 22/47] ppc/pnv: extend the machine with a XICSFabric interface, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 41/47] ppc/pnv: populate device tree for IPMI BT devices, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 38/47] ppc/pnv: scan ISA bus to populate device tree, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 33/47] ipmi: introduce an ipmi_bmc_gen_event() API, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 45/47] target/ppc: Flush TLB on write to PIDR,
David Gibson <=
- [Qemu-devel] [PULL 34/47] target/ppc: Fix size of struct PPCElfPrstatus, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 37/47] ppc/pnv: enable only one LPC bus, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 31/47] ipmi: provide support for FRUs, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 36/47] ppc/pnv: Add support for POWER8+ LPC Controller, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 39/47] ppc/pnv: populate device tree for RTC devices, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 47/47] target/ppc: Style fixes, David Gibson, 2017/04/23
- Re: [Qemu-devel] [PULL 00/47] ppc-for-2.10 queue 20170424, no-reply, 2017/04/23
- Re: [Qemu-devel] [PULL 00/47] ppc-for-2.10 queue 20170424, Peter Maydell, 2017/04/24