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[Qemu-devel] [PULL 46/47] e500, book3s: mfspr 259: Register mapped/alias
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 46/47] e500, book3s: mfspr 259: Register mapped/aliased SPRG3 user read |
Date: |
Mon, 24 Apr 2017 11:59:26 +1000 |
From: Bernhard Kaindl <address@hidden>
This patch registers mfspr 259 for Book3S and e500 family cores
following this research:
mfspr 259 provides read-only mapped user access to SPRG3(SPR 275) according to:
- PowerISA 2.02, Book III (documents implementation starting with POWER4+ @ p20)
- IBM PowerPC 970MP RISC Microprocessor User's Manual v2.1, page 48
- Amit Singh: "Mac OS X Internals: A Systems Approach" on 970 and 970FX cores:
He demonstrates mfspr 259 reading TLS data from Mac OS X on G5 on page 588
- NXP documents it in the Core Reference Manuals of: e500, e500mc and e5500
- getcpu() of the 32 & 64-bit Book3S Linux vDSOs use it to read the core number
mfspr 259 does not appear to be implemented in these cores according to:
- 74xx series: MPC7410/MPC7400 and MPC7450 RISC Microprocessor Reference Manuals
- 4xx series: PPC440 Processor User's Manual, Revision 1.09 by AMCC
- 750 series: IBM PowerPC 750CL RISC Microprocessor User's Manual
- e200 series: e200z4 Power ArchitectureĆ¢ Core Reference Manual
Implementation: gen_spr_usprg3() is called from init_proc_book3s_common()
(covers the 970 and POWER cores) and init_proc_e500() (covers the e500 family)
to register spr_read_ureg() in the same way which it already provides
the mapped SPR access for SPR_USPRG4-7 in gen_spr_usprgh() for cores
which have the same read-only mapped SPRG register access for SPRG4-7.
Verified using Linux by pinning a thread to a core and checking sched_getcpu()
using qemu-system-ppc64 -M pseries -cpu POWER8 using MTTCG on a x86_64 host.
Signed-off-by: Bernhard Kaindl <address@hidden>
Reviewed-by: Stefan Resch <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate_init.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 77e5463..0ecf541 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -1640,6 +1640,14 @@ static void spr_write_booke_pid (DisasContext *ctx, int
sprn, int gprn)
}
#endif
+static void gen_spr_usprg3 (CPUPPCState *env)
+{
+ spr_register(env, SPR_USPRG3, "USPRG3",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+}
+
static void gen_spr_usprgh (CPUPPCState *env)
{
spr_register(env, SPR_USPRG4, "USPRG4",
@@ -4914,6 +4922,7 @@ static void init_proc_e500 (CPUPPCState *env, int version)
break;
}
gen_spr_BookE(env, ivor_mask);
+ gen_spr_usprg3(env);
/* Processor identification */
spr_register(env, SPR_BOOKE_PIR, "PIR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -8245,6 +8254,7 @@ static void init_proc_book3s_common(CPUPPCState *env)
{
gen_spr_ne_601(env);
gen_tbl(env);
+ gen_spr_usprg3(env);
gen_spr_book3s_altivec(env);
gen_spr_book3s_pmu_sup(env);
gen_spr_book3s_pmu_user(env);
--
2.9.3
- [Qemu-devel] [PULL 21/47] ppc/pnv: add a PnvICPState object, (continued)
- [Qemu-devel] [PULL 21/47] ppc/pnv: add a PnvICPState object, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 27/47] ppc/pnv: Add cut down PSI bridge model and hookup external interrupt, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 30/47] ipmi: use a file to load SDRs, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 20/47] ppc/xics: add a realize() handler to ICPStateClass, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 43/47] ppc/pnv: generate an OEM SEL event on shutdown, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 42/47] ppc/pnv: add initial IPMI sensors for the BMC simulator, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 35/47] spapr: remove the 'nr_servers' field from the machine, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 17/47] ppc/xics: introduce an 'intc' backlink under PowerPCCPU, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 24/47] ppc/pnv: create the ICP object under PnvCore, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 26/47] ppc/pnv: add memory regions for the ICP registers, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 46/47] e500, book3s: mfspr 259: Register mapped/aliased SPRG3 user read,
David Gibson <=
- [Qemu-devel] [PULL 28/47] ppc/pnv: Add OCC model stub with interrupt support, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 44/47] spapr-cpu-core: Release ICPState object during CPU unrealization, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 25/47] ppc/pnv: add a helper to calculate MMIO addresses registers, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 22/47] ppc/pnv: extend the machine with a XICSFabric interface, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 41/47] ppc/pnv: populate device tree for IPMI BT devices, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 38/47] ppc/pnv: scan ISA bus to populate device tree, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 33/47] ipmi: introduce an ipmi_bmc_gen_event() API, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 45/47] target/ppc: Flush TLB on write to PIDR, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 34/47] target/ppc: Fix size of struct PPCElfPrstatus, David Gibson, 2017/04/23
- [Qemu-devel] [PULL 37/47] ppc/pnv: enable only one LPC bus, David Gibson, 2017/04/23