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[Qemu-devel] [PATCH 08/13] armv7m: Improve "-d mmu" tracing for PMSAv7 M
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 08/13] armv7m: Improve "-d mmu" tracing for PMSAv7 MPU |
Date: |
Tue, 25 Apr 2017 13:07:05 +0100 |
From: Michael Davidsaver <address@hidden>
Improve the "-d mmu" tracing for the PMSAv7 MPU translation
process as an aid in debugging guest MPU configurations:
* fix a missing newline for a guest-error log
* report the region number with guest-error or unimp
logs of bad region register values
* add a log message for the overall result of the lookup
* print "0x" prefix for hex values
Signed-off-by: Michael Davidsaver <address@hidden>
[PMM: a little tidyup, report region number in all messages
rather than just one]
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 39 +++++++++++++++++++++++++++------------
1 file changed, 27 insertions(+), 12 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 5c044d0..9e1ed1c 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8169,16 +8169,18 @@ static bool get_phys_addr_pmsav7(CPUARMState *env,
uint32_t address,
}
if (!rsize) {
- qemu_log_mask(LOG_GUEST_ERROR, "DRSR.Rsize field can not be
0");
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "DRSR[%d]: Rsize field cannot be 0\n", n);
continue;
}
rsize++;
rmask = (1ull << rsize) - 1;
if (base & rmask) {
- qemu_log_mask(LOG_GUEST_ERROR, "DRBAR %" PRIx32 " misaligned "
- "to DRSR region size, mask = %" PRIx32,
- base, rmask);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "DRBAR[%d]: 0x%" PRIx32 " misaligned "
+ "to DRSR region size, mask = 0x%" PRIx32 "\n",
+ n, base, rmask);
continue;
}
@@ -8215,9 +8217,10 @@ static bool get_phys_addr_pmsav7(CPUARMState *env,
uint32_t address,
}
}
if (rsize < TARGET_PAGE_BITS) {
- qemu_log_mask(LOG_UNIMP, "No support for MPU (sub)region"
+ qemu_log_mask(LOG_UNIMP,
+ "DRSR[%d]: No support for MPU (sub)region "
"alignment of %" PRIu32 " bits. Minimum is %d\n",
- rsize, TARGET_PAGE_BITS);
+ n, rsize, TARGET_PAGE_BITS);
continue;
}
if (srdis) {
@@ -8251,8 +8254,8 @@ static bool get_phys_addr_pmsav7(CPUARMState *env,
uint32_t address,
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
- "Bad value for AP bits in DRACR %"
- PRIx32 "\n", ap);
+ "DRACR[%d]: Bad value for AP bits: 0x%"
+ PRIx32 "\n", n, ap);
}
} else { /* Priv. mode AP bits decoding */
switch (ap) {
@@ -8269,8 +8272,8 @@ static bool get_phys_addr_pmsav7(CPUARMState *env,
uint32_t address,
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
- "Bad value for AP bits in DRACR %"
- PRIx32 "\n", ap);
+ "DRACR[%d]: Bad value for AP bits: 0x%"
+ PRIx32 "\n", n, ap);
}
}
@@ -8448,9 +8451,21 @@ static bool get_phys_addr(CPUARMState *env, target_ulong
address,
*/
if (arm_feature(env, ARM_FEATURE_PMSA) &&
arm_feature(env, ARM_FEATURE_V7)) {
+ bool ret;
*page_size = TARGET_PAGE_SIZE;
- return get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
- phys_ptr, prot, fsr);
+ ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
+ phys_ptr, prot, fsr);
+ qemu_log_mask(CPU_LOG_MMU, "PMSAv7 MPU lookup for %s at 0x%08" PRIx32
+ " mmu_idx %u -> %s (prot %c%c%c)\n",
+ access_type == 1 ? "reading" :
+ (access_type == 2 ? "writing" : "execute"),
+ (uint32_t)address, mmu_idx,
+ ret ? "Miss" : "Hit",
+ *prot & PAGE_READ ? 'r' : '-',
+ *prot & PAGE_WRITE ? 'w' : '-',
+ *prot & PAGE_EXEC ? 'x' : '-');
+
+ return ret;
}
if (regime_translation_disabled(env, mmu_idx)) {
--
2.7.4
- [Qemu-devel] [PATCH 00/13] armv7m: Implement MPU support, Peter Maydell, 2017/04/25
- [Qemu-devel] [PATCH 13/13] arm: Implement HFNMIENA support for M profile MPU, Peter Maydell, 2017/04/25
- [Qemu-devel] [PATCH 11/13] armv7m: Classify faults as MemManage or BusFault, Peter Maydell, 2017/04/25
- [Qemu-devel] [PATCH 03/13] arm: Use different ARMMMUIdx values for M profile, Peter Maydell, 2017/04/25
- [Qemu-devel] [PATCH 05/13] arm: Don't clear ARM_FEATURE_PMSA for no-mpu configs, Peter Maydell, 2017/04/25
- [Qemu-devel] [PATCH 06/13] arm: Don't let no-MPU PMSA cores write to SCTLR.M, Peter Maydell, 2017/04/25
- [Qemu-devel] [PATCH 08/13] armv7m: Improve "-d mmu" tracing for PMSAv7 MPU,
Peter Maydell <=
- [Qemu-devel] [PATCH 10/13] arm: All M profile cores are PMSA, Peter Maydell, 2017/04/25
- [Qemu-devel] [PATCH 01/13] arm: Use the mmu_idx we're passed in arm_cpu_do_unaligned_access(), Peter Maydell, 2017/04/25
- [Qemu-devel] [PATCH 02/13] arm: Add support for M profile CPUs having different MMU index semantics, Peter Maydell, 2017/04/25
- [Qemu-devel] [PATCH 04/13] arm: Clean up handling of no-MPU PMSA CPUs, Peter Maydell, 2017/04/25
- [Qemu-devel] [PATCH 09/13] armv7m: Implement M profile default memory map, Peter Maydell, 2017/04/25
- [Qemu-devel] [PATCH 07/13] arm: Remove unnecessary check on cpu->pmsav7_dregion, Peter Maydell, 2017/04/25
- [Qemu-devel] [PATCH 12/13] arm: add MPU support to M profile CPUs, Peter Maydell, 2017/04/25