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[Qemu-devel] [PATCH v3 10/15] target/sh4: optimize gen_write_sr using ex
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH v3 10/15] target/sh4: optimize gen_write_sr using extract op |
Date: |
Wed, 10 May 2017 20:26:31 +0200 |
This doesn't change the generated code on x86, but optimizes it on most
RISC architectures and makes the code simpler to read.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
---
target/sh4/translate.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index fe8bff54a6..7a504a7f5a 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -204,12 +204,9 @@ static void gen_write_sr(TCGv src)
{
tcg_gen_andi_i32(cpu_sr, src,
~((1u << SR_Q) | (1u << SR_M) | (1u << SR_T)));
- tcg_gen_shri_i32(cpu_sr_q, src, SR_Q);
- tcg_gen_andi_i32(cpu_sr_q, cpu_sr_q, 1);
- tcg_gen_shri_i32(cpu_sr_m, src, SR_M);
- tcg_gen_andi_i32(cpu_sr_m, cpu_sr_m, 1);
- tcg_gen_shri_i32(cpu_sr_t, src, SR_T);
- tcg_gen_andi_i32(cpu_sr_t, cpu_sr_t, 1);
+ tcg_gen_extract_i32(cpu_sr_q, src, SR_Q, 1);
+ tcg_gen_extract_i32(cpu_sr_m, src, SR_M, 1);
+ tcg_gen_extract_i32(cpu_sr_t, src, SR_T, 1);
}
static inline void gen_save_cpu_state(DisasContext *ctx, bool save_pc)
--
2.11.0
- [Qemu-devel] [PATCH v3 00/15] target/sh4: misc fixes, cleanup and optimizations, Aurelien Jarno, 2017/05/10
- [Qemu-devel] [PATCH v3 05/15] target/sh4: fix BS_STOP exit, Aurelien Jarno, 2017/05/10
- [Qemu-devel] [PATCH v3 03/15] target/sh4: do not include DELAY_SLOT_TRUE in the TB state, Aurelien Jarno, 2017/05/10
- [Qemu-devel] [PATCH v3 13/15] target/sh4: movua.l is an SH4-A only instruction, Aurelien Jarno, 2017/05/10
- [Qemu-devel] [PATCH v3 06/15] target/sh4: fix BS_EXCP exit, Aurelien Jarno, 2017/05/10
- [Qemu-devel] [PATCH v3 08/15] target/sh4: fold ctx->bstate = BS_BRANCH into gen_conditional_jump, Aurelien Jarno, 2017/05/10
- [Qemu-devel] [PATCH v3 14/15] target/sh4: trap unaligned accesses, Aurelien Jarno, 2017/05/10
- [Qemu-devel] [PATCH v3 02/15] target/sh4: get rid of DELAY_SLOT_CLEARME, Aurelien Jarno, 2017/05/10
- [Qemu-devel] [PATCH v3 10/15] target/sh4: optimize gen_write_sr using extract op,
Aurelien Jarno <=
- [Qemu-devel] [PATCH v3 12/15] target/sh4: implement tas.b using atomic helper, Aurelien Jarno, 2017/05/10
- [Qemu-devel] [PATCH v3 11/15] target/sh4: generate fences for SH4, Aurelien Jarno, 2017/05/10
- [Qemu-devel] [PATCH v3 04/15] target/sh4: move DELAY_SLOT_TRUE flag into a separate global, Aurelien Jarno, 2017/05/10
- [Qemu-devel] [PATCH v3 15/15] target/sh4: use cpu_loop_exit_restore, Aurelien Jarno, 2017/05/10
- [Qemu-devel] [PATCH v3 01/15] target/sh4: split ctx->flags into ctx->tbflags and ctx->envflags, Aurelien Jarno, 2017/05/10
- [Qemu-devel] [PATCH v3 09/15] target/sh4: optimize gen_store_fpr64, Aurelien Jarno, 2017/05/10
- [Qemu-devel] [PATCH v3 07/15] target/sh4: only save flags state at the end of the TB, Aurelien Jarno, 2017/05/10