Re: [Qemu-devel] [PATCH v2 3/5] target/mips: Exit after enabling interrupts

[Aurelien Jarno]

On 2017-06-14 12:48, Richard Henderson wrote:
> From: Paolo Bonzini <address@hidden>
> 
> Exit to cpu loop so we reevaluate cpu_mips_hw_interrupts.
> 
> Cc: Aurelien Jarno <address@hidden>
> Cc: Yongbok Kim <address@hidden>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
>  target/mips/translate.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 559f8fe..891f14b 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -13403,9 +13403,11 @@ static void gen_pool32axf (CPUMIPSState *env, 
> DisasContext *ctx, int rt, int rs)
>                  save_cpu_state(ctx, 1);
>                  gen_helper_ei(t0, cpu_env);
>                  gen_store_gpr(t0, rs);
> -                /* Stop translation as we may have switched the execution 
> mode */
> -                ctx->bstate = BS_STOP;
>                  tcg_temp_free(t0);
> +                /* BS_STOP isn't good enough here;
> +                   reevaluate cpu_mips_hw_interrupts_enabled.  */
> +                gen_save_pc(ctx->pc + 4);
> +                ctx->bstate = BS_EXCP;
>              }
>              break;
>          default:

While the above looks correct, it's not complete. It only fixes the
microMIPS EI instruction. The MIPS one also has to be fixed.

For what I understood, anything that can change the result of
cpu_mips_hw_interrupts_enabled has to stop the translation. In that case
I checked that ERET/ERETNC and MTC0/DMTC0 to the Status register are
already correct, that said it might be a good idea to update the
comments to mention it.

I can work on a better patch, but I doubt I'll have time before the
week-end.

Aurelien

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
address@hidden                 http://www.aurel32.net