[Qemu-devel] [Intel-gfx][RFC 5/9] drm/i915/gvt: Align the guest gm aperture start offset for live migration

[Yulei Zhang]

As guest gm aperture region start offset is initialized when vGPU created,
in order to make sure that start offset is remain the same after migration,
align the aperture start offset to 0 for guest.

Signed-off-by: Yulei Zhang <address@hidden>
---
 drivers/gpu/drm/i915/gvt/kvmgt.c | 3 +--
 drivers/gpu/drm/i915/gvt/vgpu.c  | 7 +++++--
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 1ae0b40..d2b13ae 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -1002,8 +1002,7 @@ static long intel_vgpu_ioctl(struct mdev_device *mdev, 
unsigned int cmd,
 
                        sparse->nr_areas = nr_areas;
                        cap_type_id = VFIO_REGION_INFO_CAP_SPARSE_MMAP;
-                       sparse->areas[0].offset =
-                                       PAGE_ALIGN(vgpu_aperture_offset(vgpu));
+                       sparse->areas[0].offset = 0;
                        sparse->areas[0].size = vgpu_aperture_sz(vgpu);
                        break;
 
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index 90c14e6..989f353 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -43,8 +43,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
        vgpu_vreg(vgpu, vgtif_reg(version_minor)) = 0;
        vgpu_vreg(vgpu, vgtif_reg(display_ready)) = 0;
        vgpu_vreg(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
-       vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
-               vgpu_aperture_gmadr_base(vgpu);
+       vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) = 0;
        vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
                vgpu_aperture_sz(vgpu);
        vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
@@ -480,6 +479,8 @@ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, 
bool dmlr,
 {
        struct intel_gvt *gvt = vgpu->gvt;
        struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
+       u64 maddr = vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base));
+       u64 unmaddr = vgpu_vreg(vgpu, 
vgtif_reg(avail_rs.nonmappable_gmadr.base));
 
        gvt_dbg_core("------------------------------------------\n");
        gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n",
@@ -510,6 +511,8 @@ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, 
bool dmlr,
 
                intel_vgpu_reset_mmio(vgpu, dmlr);
                populate_pvinfo_page(vgpu);
+               vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) = 
maddr;
+               vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) = 
unmaddr;
                intel_vgpu_reset_display(vgpu);
 
                if (dmlr) {
-- 
2.7.4