[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL v1 14/17] target-microblaze: dec_barrel: Add BSEFI
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PULL v1 14/17] target-microblaze: dec_barrel: Add BSEFI |
Date: |
Tue, 4 Jul 2017 11:54:45 +0200 |
From: "Edgar E. Iglesias" <address@hidden>
Add support for BSEFI.
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target/microblaze/translate.c | 42 ++++++++++++++++++++++++++++++------------
1 file changed, 30 insertions(+), 12 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 6ee4885..3fad13c 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -660,7 +660,8 @@ static void dec_div(DisasContext *dc)
static void dec_barrel(DisasContext *dc)
{
TCGv t0;
- bool s, t;
+ unsigned int imm_w, imm_s;
+ bool s, t, e = false;
if ((dc->tb_flags & MSR_EE_FLAG)
&& (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
@@ -670,27 +671,44 @@ static void dec_barrel(DisasContext *dc)
return;
}
+ if (dc->type_b) {
+ /* Insert and extract are only available in immediate mode. */
+ e = extract32(dc->imm, 14, 1);
+ }
s = extract32(dc->imm, 10, 1);
t = extract32(dc->imm, 9, 1);
+ imm_w = extract32(dc->imm, 6, 5);
+ imm_s = extract32(dc->imm, 0, 5);
- LOG_DIS("bs%s%s r%d r%d r%d\n",
+ LOG_DIS("bs%s%s%s r%d r%d r%d\n",
+ e ? "e" : "",
s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb);
- t0 = tcg_temp_new();
+ if (e) {
+ if (imm_w + imm_s > 32 || imm_w == 0) {
+ /* These inputs have an undefined behavior. */
+ qemu_log_mask(LOG_GUEST_ERROR, "bsefi: Bad input w=%d s=%d\n",
+ imm_w, imm_s);
+ } else {
+ tcg_gen_extract_i32(cpu_R[dc->rd], cpu_R[dc->ra], imm_s, imm_w);
+ }
+ } else {
+ t0 = tcg_temp_new();
- tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc)));
- tcg_gen_andi_tl(t0, t0, 31);
+ tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc)));
+ tcg_gen_andi_tl(t0, t0, 31);
- if (s) {
- tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
- } else {
- if (t) {
- tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
+ if (s) {
+ tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
} else {
- tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
+ if (t) {
+ tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
+ } else {
+ tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
+ }
}
+ tcg_temp_free(t0);
}
- tcg_temp_free(t0);
}
static void dec_bit(DisasContext *dc)
--
2.7.4
- [Qemu-devel] [PULL v1 03/17] target-microblaze: Don't hard code 0xb as initial MB version, (continued)
- [Qemu-devel] [PULL v1 03/17] target-microblaze: Don't hard code 0xb as initial MB version, Edgar E. Iglesias, 2017/07/04
- [Qemu-devel] [PULL v1 05/17] target-microblaze: Introduce a use-barrel property, Edgar E. Iglesias, 2017/07/04
- [Qemu-devel] [PULL v1 06/17] target-microblaze: Introduce a use-div property, Edgar E. Iglesias, 2017/07/04
- [Qemu-devel] [PULL v1 07/17] target-microblaze: Introduce a use-hw-mul property, Edgar E. Iglesias, 2017/07/04
- [Qemu-devel] [PULL v1 09/17] target-microblaze: Introduce a use-pcmp-instr property, Edgar E. Iglesias, 2017/07/04
- [Qemu-devel] [PULL v1 10/17] target-microblaze: dec_barrel: Use bool instead of unsigned int, Edgar E. Iglesias, 2017/07/04
- [Qemu-devel] [PULL v1 11/17] target-microblaze: dec_barrel: Use extract32, Edgar E. Iglesias, 2017/07/04
- [Qemu-devel] [PULL v1 13/17] target-microblaze: dec_barrel: Plug TCG temp leak, Edgar E. Iglesias, 2017/07/04
- [Qemu-devel] [PULL v1 08/17] target-microblaze: Introduce a use-msr-instr property, Edgar E. Iglesias, 2017/07/04
- [Qemu-devel] [PULL v1 12/17] target-microblaze: dec_barrel: Add braces around if-statements, Edgar E. Iglesias, 2017/07/04
- [Qemu-devel] [PULL v1 14/17] target-microblaze: dec_barrel: Add BSEFI,
Edgar E. Iglesias <=
- [Qemu-devel] [PULL v1 15/17] target-microblaze: dec_barrel: Add BSIFI, Edgar E. Iglesias, 2017/07/04
- [Qemu-devel] [PULL v1 16/17] target-microblaze: Add CPU version 10.0, Edgar E. Iglesias, 2017/07/04
- [Qemu-devel] [PULL v1 17/17] xilinx-dp: Add support for the yuy2 video format, Edgar E. Iglesias, 2017/07/04
- Re: [Qemu-devel] [PULL v1 00/17] Xilinx queue, Peter Maydell, 2017/07/04