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[Qemu-devel] [PATCH 10/11] target/sh4: Hoist fp bank selection
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 10/11] target/sh4: Hoist fp bank selection |
Date: |
Wed, 5 Jul 2017 14:24:00 -1000 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/sh4/translate.c | 34 +++++++++++++++++++++++-----------
1 file changed, 23 insertions(+), 11 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 7f015c3..a45d0ee 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -37,6 +37,7 @@ typedef struct DisasContext {
struct TranslationBlock *tb;
TCGv *gregs; /* active bank */
TCGv *altregs; /* inactive, alternate, bank */
+ TCGv *fregs; /* active bank */
target_ulong pc;
uint16_t opcode;
uint32_t tbflags; /* should stay unmodified during the TB translation */
@@ -72,7 +73,7 @@ static TCGv cpu_pc, cpu_ssr, cpu_spc, cpu_gbr;
static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl;
static TCGv cpu_pr, cpu_fpscr, cpu_fpul;
static TCGv cpu_lock_addr, cpu_lock_value;
-static TCGv cpu_fregs[32];
+static TCGv cpu_fregs[2][16];
/* internal register indexes */
static TCGv cpu_flags, cpu_delayed_pc, cpu_delayed_cond;
@@ -176,10 +177,18 @@ void sh4_translate_init(void)
offsetof(CPUSH4State, lock_value),
"_lock_value_");
- for (i = 0; i < 32; i++)
- cpu_fregs[i] = tcg_global_mem_new_i32(cpu_env,
- offsetof(CPUSH4State, fregs[i]),
- fregnames[i]);
+ for (i = 0; i < 16; i++) {
+ cpu_fregs[0][i]
+ = tcg_global_mem_new_i32(cpu_env,
+ offsetof(CPUSH4State, fregs[i]),
+ fregnames[i]);
+ }
+ for (i = 16; i < 32; i++) {
+ cpu_fregs[1][i - 16]
+ = tcg_global_mem_new_i32(cpu_env,
+ offsetof(CPUSH4State, fregs[i]),
+ fregnames[i]);
+ }
done_init = 1;
}
@@ -365,12 +374,12 @@ static void gen_delayed_conditional_jump(DisasContext *
ctx)
low register means we can't crash the translator for REG==15. */
static void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
{
- tcg_gen_concat_i32_i64(t, cpu_fregs[reg | 1], cpu_fregs[reg]);
+ tcg_gen_concat_i32_i64(t, ctx->fregs[reg | 1], ctx->fregs[reg]);
}
static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
{
- tcg_gen_extr_i64_i32(cpu_fregs[reg | 1], cpu_fregs[reg], t);
+ tcg_gen_extr_i64_i32(ctx->fregs[reg | 1], ctx->fregs[reg], t);
}
#define B3_0 (ctx->opcode & 0xf)
@@ -386,10 +395,10 @@ static void gen_store_fpr64(DisasContext *ctx, TCGv_i64
t, int reg)
#define REG(x) ctx->gregs[x]
#define ALTREG(x) ctx->altregs[x]
-#define FREG(x) cpu_fregs[ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x)]
-#define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe))
-#define XREG(x) FREG(XHACK(x))
-#define DREG(x) (ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x))
+#define FREG(x) ctx->fregs[x]
+#define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe))
+#define XREG(x) FREG(XHACK(x))
+#define DREG(x) (x)
#define CHECK_NOT_DELAY_SLOT \
if (ctx->envflags & DELAY_SLOT_MASK) { \
@@ -2230,6 +2239,9 @@ void gen_intermediate_code(CPUSH4State * env, struct
TranslationBlock *tb)
ctx.gregs = cpu_gregs[bank];
ctx.altregs = cpu_gregs[bank ^ 1];
+ bank = (ctx.tbflags & FPSCR_FR) != 0;
+ ctx.fregs = cpu_fregs[bank];
+
max_insns = tb->cflags & CF_COUNT_MASK;
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
--
2.9.4
Re: [Qemu-devel] [PATCH 05/11] linux-user/sh4: Notice gUSA regions during signal delivery, Laurent Vivier, 2017/07/06
[Qemu-devel] [PATCH 04/11] target/sh4: Recognize common gUSA sequences, Richard Henderson, 2017/07/05
[Qemu-devel] [PATCH 06/11] target/sh4: Hoist register bank selection, Richard Henderson, 2017/07/05
[Qemu-devel] [PATCH 07/11] target/sh4: Unify cpu_fregs into FREG, Richard Henderson, 2017/07/05
[Qemu-devel] [PATCH 08/11] target/sh4: Pass DisasContext to fpr64 routines, Richard Henderson, 2017/07/05
[Qemu-devel] [PATCH 10/11] target/sh4: Hoist fp bank selection,
Richard Henderson <=
[Qemu-devel] [PATCH 09/11] target/sh4: Avoid a potential translator crash for malformed FPR64, Richard Henderson, 2017/07/05
[Qemu-devel] [PATCH 11/11] target/sh4: Eliminate DREG macro, Richard Henderson, 2017/07/05
Re: [Qemu-devel] [PATCH 00/11] target/sh4 improvments, Laurent Vivier, 2017/07/05
Re: [Qemu-devel] [PATCH 00/11] target/sh4 improvments, Aurelien Jarno, 2017/07/06