[Qemu-devel] [PATCH] target/i386: Fix ANDN (bmi)

[Ricardo Ribalda Delgado]

Operands on ANDN are swapped.

Tested with the following function:

long test_andn(long v1, long v2){
        return (~v1 & v2);
}

Compiled with:

gcc kk.c -mbmi -O3 -Wall

0000000000000910 <test_andn>:
 910:c4 e2 c0 f2 c6             andn   %rsi,%rdi,%rax
 915:c3                         retq
 916:66 2e 0f 1f 84 00 00       nopw   %cs:0x0(%rax,%rax,1)
 91d:00 00 00

and

gcc kk.c -march=native -O3 -Wall

0000000000000930 <test_andn>:
 930:   48 f7 d7                not    %rdi
 933:   48 89 f8                mov    %rdi,%rax
 936:   48 21 f0                and    %rsi,%rax
 939:   c3                      retq
 93a:   66 0f 1f 44 00 00       nopw   0x0(%rax,%rax,1)

The test showed than -mbmi version behaved differently than the
-march native version.

Signed-off-by: Ricardo Ribalda Delgado <address@hidden>
---
 target/i386/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/i386/translate.c b/target/i386/translate.c
index 203623ef884c..1f39b497c19a 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -3774,7 +3774,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, 
int b,
                 }
                 ot = mo_64_32(s->dflag);
                 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
-                tcg_gen_andc_tl(cpu_T0, cpu_regs[s->vex_v], cpu_T0);
+                tcg_gen_andc_tl(cpu_T0, cpu_T0, cpu_regs[s->vex_v]);
                 gen_op_mov_reg_v(ot, reg, cpu_T0);
                 gen_op_update1_cc();
                 set_cc_op(s, CC_OP_LOGICB + ot);
-- 
2.13.2