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[Qemu-devel] [PULL 17/31] target/sh4: Hoist fp register bank selection
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PULL 17/31] target/sh4: Hoist fp register bank selection |
Date: |
Tue, 18 Jul 2017 23:50:36 +0200 |
From: Richard Henderson <address@hidden>
Compute which register bank to use once at the start of translation.
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
---
target/sh4/translate.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index b706a6a153..bc6f33970b 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -42,6 +42,7 @@ typedef struct DisasContext {
int bstate;
int memidx;
int gbank;
+ int fbank;
uint32_t delayed_pc;
int singlestep_enabled;
uint32_t features;
@@ -353,12 +354,12 @@ static inline void gen_store_fpr64(DisasContext *ctx,
TCGv_i64 t, int reg)
#define REG(x) cpu_gregs[(x) ^ ctx->gbank]
#define ALTREG(x) cpu_gregs[(x) ^ ctx->gbank ^ 0x10]
+#define FREG(x) cpu_fregs[(x) ^ ctx->fbank]
-#define FREG(x) cpu_fregs[ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x)]
#define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe))
-#define XREG(x) FREG(XHACK(x))
+#define XREG(x) FREG(XHACK(x))
/* Assumes lsb of (x) is always 0 */
-#define DREG(x) (ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x))
+#define DREG(x) ((x) ^ ctx->fbank)
#define CHECK_NOT_DELAY_SLOT \
if (ctx->envflags & DELAY_SLOT_MASK) { \
@@ -2232,6 +2233,7 @@ void gen_intermediate_code(CPUSH4State * env, struct
TranslationBlock *tb)
ctx.has_movcal = (ctx.tbflags & TB_FLAG_PENDING_MOVCA);
ctx.gbank = ((ctx.tbflags & (1 << SR_MD)) &&
(ctx.tbflags & (1 << SR_RB))) * 0x10;
+ ctx.fbank = ctx.tbflags & FPSCR_FR ? 0x10 : 0;
max_insns = tb->cflags & CF_COUNT_MASK;
if (max_insns == 0) {
--
2.11.0
- [Qemu-devel] [PULL 02/31] target/sh4: fix FPU unorderered compare, (continued)
- [Qemu-devel] [PULL 02/31] target/sh4: fix FPU unorderered compare, Aurelien Jarno, 2017/07/18
- [Qemu-devel] [PULL 07/31] target/sh4: Introduce TB_FLAG_ENVFLAGS_MASK, Aurelien Jarno, 2017/07/18
- [Qemu-devel] [PULL 19/31] target/sh4: Merge DREG into fpr64 routines, Aurelien Jarno, 2017/07/18
- [Qemu-devel] [PULL 24/31] target/sh4: Unify code for CHECK_FPU_ENABLED, Aurelien Jarno, 2017/07/18
- [Qemu-devel] [PULL 01/31] target/sh4: do not check for PR bit for fabs instruction, Aurelien Jarno, 2017/07/18
- [Qemu-devel] [PULL 26/31] target/sh4: Introduce CHECK_FPSCR_PR_*, Aurelien Jarno, 2017/07/18
- [Qemu-devel] [PULL 21/31] target/sh4: Simplify 64-bit fp reg-reg move, Aurelien Jarno, 2017/07/18
- [Qemu-devel] [PULL 06/31] target/sh4: Consolidate end-of-TB tests, Aurelien Jarno, 2017/07/18
- [Qemu-devel] [PULL 13/31] linux-user/sh4: Clean env->flags on signal boundaries, Aurelien Jarno, 2017/07/18
- [Qemu-devel] [PULL 30/31] target/sh4: Implement fsrra, Aurelien Jarno, 2017/07/18
- [Qemu-devel] [PULL 17/31] target/sh4: Hoist fp register bank selection,
Aurelien Jarno <=
- [Qemu-devel] [PULL 25/31] target/sh4: Tidy misc illegal insn checks, Aurelien Jarno, 2017/07/18
- [Qemu-devel] [PULL 05/31] target/sh4: return result of fcmp using TCG, Aurelien Jarno, 2017/07/18
- [Qemu-devel] [PULL 31/31] target/sh4: Use tcg_gen_lookup_and_goto_ptr, Aurelien Jarno, 2017/07/18
- [Qemu-devel] [PULL 29/31] target/sh4: Add missing FPSCR.PR == 0 checks, Aurelien Jarno, 2017/07/18
- [Qemu-devel] [PULL 20/31] target/sh4: Load/store Dr as 64-bit quantities, Aurelien Jarno, 2017/07/18
- [Qemu-devel] [PULL 10/31] target/sh4: Handle user-space atomics, Aurelien Jarno, 2017/07/18
- [Qemu-devel] [PULL 28/31] target/sh4: Implement fpchg, Aurelien Jarno, 2017/07/18
- [Qemu-devel] [PULL 04/31] target/sh4: do not use a helper to implement fneg, Aurelien Jarno, 2017/07/18
- [Qemu-devel] [PULL 22/31] target/sh4: Unify code for CHECK_NOT_DELAY_SLOT, Aurelien Jarno, 2017/07/18
- [Qemu-devel] [PULL 03/31] target/sh4: fix FPSCR cause vs flag inversion, Aurelien Jarno, 2017/07/18