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[Qemu-devel] [PULL 3/8] mips: Improve segment defs for KVM T&E guests
From: |
Yongbok Kim |
Subject: |
[Qemu-devel] [PULL 3/8] mips: Improve segment defs for KVM T&E guests |
Date: |
Thu, 3 Aug 2017 15:45:10 +0100 |
From: James Hogan <address@hidden>
Improve the segment definitions used by get_physical_address() to yield
target_ulong types, e.g. 0xffffffff80000000 instead of 0x80000000. This
is in preparation for enabling emulation of MIPS KVM T&E segments in TCG
MIPS targets, which unlike KVM could potentially have 64-bit
target_ulong. In such a case the offset guest KSEG0 address ends up at
e.g. 0x000000008xxxxxxx instead of 0xffffffff8xxxxxxx.
This also allows the casts to int32_t that force sign extension to be
removed, which removes any confusion due to relational comparison of
unsigned (target_ulong) and signed (int32_t) types.
Signed-off-by: James Hogan <address@hidden>
Cc: Yongbok Kim <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Cc: Paolo Bonzini <address@hidden>
Cc: address@hidden
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
---
target/mips/helper.c | 23 +++++++++++------------
1 file changed, 11 insertions(+), 12 deletions(-)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index a2b79e8..05883b9 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -216,14 +216,14 @@ static int get_physical_address (CPUMIPSState *env,
hwaddr *physical,
/* effective address (modified for KVM T&E kernel segments) */
target_ulong address = real_address;
-#define USEG_LIMIT 0x7FFFFFFFUL
-#define KSEG0_BASE 0x80000000UL
-#define KSEG1_BASE 0xA0000000UL
-#define KSEG2_BASE 0xC0000000UL
-#define KSEG3_BASE 0xE0000000UL
+#define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL)
+#define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL)
+#define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL)
+#define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL)
+#define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL)
-#define KVM_KSEG0_BASE 0x40000000UL
-#define KVM_KSEG2_BASE 0x60000000UL
+#define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL)
+#define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL)
if (kvm_enabled()) {
/* KVM T&E adds guest kernel segments in useg */
@@ -307,17 +307,17 @@ static int get_physical_address (CPUMIPSState *env,
hwaddr *physical,
ret = TLBRET_BADADDR;
}
#endif
- } else if (address < (int32_t)KSEG1_BASE) {
+ } else if (address < KSEG1_BASE) {
/* kseg0 */
ret = get_segctl_physical_address(env, physical, prot, real_address,
rw,
access_type, mmu_idx,
env->CP0_SegCtl1 >> 16, 0x1FFFFFFF);
- } else if (address < (int32_t)KSEG2_BASE) {
+ } else if (address < KSEG2_BASE) {
/* kseg1 */
ret = get_segctl_physical_address(env, physical, prot, real_address,
rw,
access_type, mmu_idx,
env->CP0_SegCtl1, 0x1FFFFFFF);
- } else if (address < (int32_t)KSEG3_BASE) {
+ } else if (address < KSEG3_BASE) {
/* sseg (kseg2) */
ret = get_segctl_physical_address(env, physical, prot, real_address,
rw,
access_type, mmu_idx,
@@ -974,8 +974,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
} else if (cause == 30 && !(env->CP0_Config3 & (1 << CP0C3_SC) &&
env->CP0_Config5 & (1 << CP0C5_CV))) {
/* Force KSeg1 for cache errors */
- env->active_tc.PC = (int32_t)KSEG1_BASE |
- (env->CP0_EBase & 0x1FFFF000);
+ env->active_tc.PC = KSEG1_BASE | (env->CP0_EBase & 0x1FFFF000);
} else {
env->active_tc.PC = env->CP0_EBase & ~0xfff;
}
--
2.7.4
- [Qemu-devel] [PULL 0/8] target-mips queue, Yongbok Kim, 2017/08/03
- [Qemu-devel] [PULL 2/8] mips/malta: leave space for the bootmap after the initrd, Yongbok Kim, 2017/08/03
- [Qemu-devel] [PULL 1/8] target-mips: Don't stop on [d]mtc0 DESAVE/KScratch, Yongbok Kim, 2017/08/03
- [Qemu-devel] [PULL 7/8] target/mips: Drop redundant gen_io_start/stop(), Yongbok Kim, 2017/08/03
- [Qemu-devel] [PULL 5/8] target-mips: apply CP0.PageMask before writing into TLB entry, Yongbok Kim, 2017/08/03
- [Qemu-devel] [PULL 4/8] mips: Add KVM T&E segment support for TCG, Yongbok Kim, 2017/08/03
- [Qemu-devel] [PULL 3/8] mips: Improve segment defs for KVM T&E guests,
Yongbok Kim <=
- [Qemu-devel] [PULL 8/8] target/mips: Fix RDHWR CC with icount, Yongbok Kim, 2017/08/03
- [Qemu-devel] [PULL 6/8] target/mips: Use BS_EXCP where interrupts are expected, Yongbok Kim, 2017/08/03
- Re: [Qemu-devel] [PULL 0/8] target-mips queue, Peter Maydell, 2017/08/04