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[Qemu-devel] [PULL 22/31] target/arm: Make MPU_CTRL register banked for
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 22/31] target/arm: Make MPU_CTRL register banked for v8M |
Date: |
Thu, 7 Sep 2017 14:28:15 +0100 |
Make the MPU_CTRL register banked if v8M security extensions are
enabled.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/cpu.h | 2 +-
hw/intc/armv7m_nvic.c | 9 +++++----
target/arm/helper.c | 5 +++--
target/arm/machine.c | 3 ++-
4 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 425adc3..29ffb26 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -429,7 +429,7 @@ typedef struct CPUARMState {
uint32_t dfsr; /* Debug Fault Status Register */
uint32_t mmfar; /* MemManage Fault Address */
uint32_t bfar; /* BusFault Address */
- unsigned mpu_ctrl; /* MPU_CTRL */
+ unsigned mpu_ctrl[2]; /* MPU_CTRL */
int exception;
uint32_t primask[2];
uint32_t faultmask[2];
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index c3c214c..a4c298f 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -541,7 +541,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset,
MemTxAttrs attrs)
return cpu->pmsav7_dregion << 8;
break;
case 0xd94: /* MPU_CTRL */
- return cpu->env.v7m.mpu_ctrl;
+ return cpu->env.v7m.mpu_ctrl[attrs.secure];
case 0xd98: /* MPU_RNR */
return cpu->env.pmsav7.rnr[attrs.secure];
case 0xd9c: /* MPU_RBAR */
@@ -720,9 +720,10 @@ static void nvic_writel(NVICState *s, uint32_t offset,
uint32_t value,
qemu_log_mask(LOG_GUEST_ERROR, "MPU_CTRL: HFNMIENA and !ENABLE is "
"UNPREDICTABLE\n");
}
- cpu->env.v7m.mpu_ctrl = value & (R_V7M_MPU_CTRL_ENABLE_MASK |
- R_V7M_MPU_CTRL_HFNMIENA_MASK |
- R_V7M_MPU_CTRL_PRIVDEFENA_MASK);
+ cpu->env.v7m.mpu_ctrl[attrs.secure]
+ = value & (R_V7M_MPU_CTRL_ENABLE_MASK |
+ R_V7M_MPU_CTRL_HFNMIENA_MASK |
+ R_V7M_MPU_CTRL_PRIVDEFENA_MASK);
tlb_flush(CPU(cpu));
break;
case 0xd98: /* MPU_RNR */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 4db191e..cc68688 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7091,7 +7091,7 @@ static inline bool
regime_translation_disabled(CPUARMState *env,
ARMMMUIdx mmu_idx)
{
if (arm_feature(env, ARM_FEATURE_M)) {
- switch (env->v7m.mpu_ctrl &
+ switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] &
(R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) {
case R_V7M_MPU_CTRL_ENABLE_MASK:
/* Enabled, but not for HardFault and NMI */
@@ -8251,7 +8251,8 @@ static bool pmsav7_use_background_region(ARMCPU *cpu,
}
if (arm_feature(env, ARM_FEATURE_M)) {
- return env->v7m.mpu_ctrl & R_V7M_MPU_CTRL_PRIVDEFENA_MASK;
+ return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)]
+ & R_V7M_MPU_CTRL_PRIVDEFENA_MASK;
} else {
return regime_sctlr(env, mmu_idx) & SCTLR_BR;
}
diff --git a/target/arm/machine.c b/target/arm/machine.c
index 7f894e5..666655d 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -123,7 +123,7 @@ static const VMStateDescription vmstate_m = {
VMSTATE_UINT32(env.v7m.dfsr, ARMCPU),
VMSTATE_UINT32(env.v7m.mmfar, ARMCPU),
VMSTATE_UINT32(env.v7m.bfar, ARMCPU),
- VMSTATE_UINT32(env.v7m.mpu_ctrl, ARMCPU),
+ VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_NS], ARMCPU),
VMSTATE_INT32(env.v7m.exception, ARMCPU),
VMSTATE_END_OF_LIST()
},
@@ -270,6 +270,7 @@ static const VMStateDescription vmstate_m_security = {
0, vmstate_info_uint32, uint32_t),
VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU),
VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate),
+ VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU),
VMSTATE_END_OF_LIST()
}
};
--
2.7.4
- [Qemu-devel] [PULL 03/31] gicv3: Convert to DEFINE_PROP_LINK, (continued)
- [Qemu-devel] [PULL 03/31] gicv3: Convert to DEFINE_PROP_LINK, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 21/31] target/arm: Make MPU_RNR register banked for v8M, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 08/31] target/arm: Implement ARMv8M's PMSAv8 registers, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 19/31] target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 06/31] xilinx_axidma: Convert to DEFINE_PROP_LINK, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 25/31] target/arm: Make CFSR register banked for v8M, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 23/31] target/arm: Make CCR register banked for v8M, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 16/31] target/arm: Make CONTROL register banked for v8M, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 26/31] target/arm: Move regime_is_secure() to target/arm/internals.h, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 24/31] target/arm: Make MMFAR banked for v8M, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 22/31] target/arm: Make MPU_CTRL register banked for v8M,
Peter Maydell <=
- [Qemu-devel] [PULL 02/31] armv7m: Convert armv7m.memory to DEFINE_PROP_LINK, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 28/31] boards.h: Define new flag ignore_memory_transaction_failures, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 29/31] hw/arm: Set ignore_memory_transaction_failures for most ARM boards, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 05/31] xilinx_axienet: Convert to DEFINE_PROP_LINK, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 31/31] target/arm: Add Jazelle feature, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 30/31] target/arm: Implement new do_transaction_failed hook, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 27/31] target/arm: Implement BXNS, and banked stack pointers, Peter Maydell, 2017/09/07
- Re: [Qemu-devel] [PULL 00/31] target-arm queue, Peter Maydell, 2017/09/07
- [Qemu-devel] [PULL 00/31] target-arm queue, Peter Maydell, 2017/09/21