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[Qemu-devel] [PULL 04/20] nvic: Clear the vector arrays and prigroup on
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 04/20] nvic: Clear the vector arrays and prigroup on reset |
Date: |
Fri, 6 Oct 2017 16:59:29 +0100 |
Reset for devices does not include an automatic clear of the
device state (unlike CPU state, where most of the state
structure is cleared to zero). Add some missing initialization
of NVIC state that meant that the device was left in the wrong
state if the guest did a warm reset.
(In particular, since we were resetting the computed state like
s->exception_prio but not all the state it was computed
from like s->vectors[x].active, the NVIC wound up in an
inconsistent state that could later trigger assertion failures.)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
---
hw/intc/armv7m_nvic.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index d90d8d0..bc7b66d 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -1782,6 +1782,11 @@ static void armv7m_nvic_reset(DeviceState *dev)
int resetprio;
NVICState *s = NVIC(dev);
+ memset(s->vectors, 0, sizeof(s->vectors));
+ memset(s->sec_vectors, 0, sizeof(s->sec_vectors));
+ s->prigroup[M_REG_NS] = 0;
+ s->prigroup[M_REG_S] = 0;
+
s->vectors[ARMV7M_EXCP_NMI].enabled = 1;
/* MEM, BUS, and USAGE are enabled through
* the System Handler Control register
--
2.7.4
- [Qemu-devel] [PULL 14/20] target/arm: Add support for restoring v8M additional state context, (continued)
- [Qemu-devel] [PULL 14/20] target/arm: Add support for restoring v8M additional state context, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 16/20] nvic: Implement Security Attribution Unit registers, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 09/20] target/arm: Check for xPSR mismatch usage faults earlier for v8M, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 18/20] target/arm: Fix calculation of secure mm_idx values, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 15/20] target/arm: Add v8M support to exception entry code, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 12/20] target/arm: Add new-in-v8M SFSR and SFAR, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 10/20] target/arm: Warn about restoring to unaligned stack, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 11/20] target/arm: Don't warn about exception return with PC low bit set for v8M, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 08/20] target/arm: Restore SPSEL to correct CONTROL register on exception return, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 03/20] hw/arm/xlnx-zynqmp: Mark the "xlnx, zynqmp" device with user_creatable = false, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 04/20] nvic: Clear the vector arrays and prigroup on reset,
Peter Maydell <=
- [Qemu-devel] [PULL 20/20] nvic: Add missing code for writing SHCSR.HARDFAULTPENDED bit, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 02/20] hw/sd: fix out-of-bounds check for multi block reads, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 07/20] target/arm: Restore security state on exception return, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 19/20] target/arm: Factor out "get mmuidx for specified security state", Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 17/20] target/arm: Implement security attribute lookups for memory accesses, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 01/20] arm: Fix SMC reporting to EL2 when QEMU provides PSCI, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 05/20] target/arm: Don't switch to target stack early in v7M exception return, Peter Maydell, 2017/10/06
- [Qemu-devel] [PULL 06/20] target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode, Peter Maydell, 2017/10/06
- Re: [Qemu-devel] [PULL 00/20] target-arm queue, Peter Maydell, 2017/10/06