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Re: [Qemu-devel] [RFC PATCH 23/30] softfloat: add float16_rem and float1
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [RFC PATCH 23/30] softfloat: add float16_rem and float16_muladd (!CHECK) |
Date: |
Mon, 16 Oct 2017 19:17:23 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 |
On 10/13/2017 09:24 AM, Alex Bennée wrote:
> +float16 float16_rem(float16 a, float16 b, float_status *status)
> +{
> + flag aSign, zSign;
> + int aExp, bExp, expDiff;
> + uint32_t aSig, bSig;
> + uint32_t q;
> + uint64_t aSig64, bSig64, q64;
> + uint32_t alternateASig;
> + int32_t sigMean;
> + a = float16_squash_input_denormal(a, status);
> + b = float16_squash_input_denormal(b, status);
> +
> + aSig = extractFloat32Frac( a );
> + aExp = extractFloat32Exp( a );
> + aSign = extractFloat32Sign( a );
> + bSig = extractFloat32Frac( b );
> + bExp = extractFloat32Exp( b );
> + if ( aExp == 0xFF ) {
> + if ( aSig || ( ( bExp == 0xFF ) && bSig ) ) {
> + return propagateFloat32NaN(a, b, status);
> + }
> + float_raise(float_flag_invalid, status);
> + return float16_default_nan(status);
> + }
> + if ( bExp == 0xFF ) {
> + if (bSig) {
> + return propagateFloat32NaN(a, b, status);
> + }
> + return a;
> + }
s/0xff/0x1f/.
> + if ( bExp == 0 ) {
> + if ( bSig == 0 ) {
> + float_raise(float_flag_invalid, status);
> + return float16_default_nan(status);
> + }
> + normalizeFloat32Subnormal( bSig, &bExp, &bSig );
> + }
> + if ( aExp == 0 ) {
> + if ( aSig == 0 ) return a;
> + normalizeFloat32Subnormal( aSig, &aExp, &aSig );
> + }
> + expDiff = aExp - bExp;
> + aSig |= 0x00800000;
> + bSig |= 0x00800000;
These implicit bits are set for float32.
> + if ( expDiff < 32 ) {
> + aSig <<= 8;
> + bSig <<= 8;
This algorithm isn't going to work unless the fractions are normalized to
0b1xxx_xxxx_xxx0_0000, just like for float32. Indeed, I think you should
actually share code.
> + return normalizeRoundAndPackFloat32(aSign ^ zSign, bExp, aSig, status);
... but you really will have to pack into the correct format.
> + if (((aExp == 0xff) && aSig) ||
> + ((bExp == 0xff) && bSig) ||
> + ((cExp == 0xff) && cSig)) {
0x1f, lots more times.
> + /* Calculate the actual result a * b + c */
> +
> + /* Multiply first; this is easy. */
> + /* NB: we subtract 0x7e where float16_mul() subtracts 0x7f
> + * because we want the true exponent, not the "one-less-than"
> + * flavour that roundAndPackFloat16() takes.
> + */
> + pExp = aExp + bExp - 0x7e;
> + aSig = (aSig | 0x00800000) << 7;
> + bSig = (bSig | 0x00800000) << 8;
All of these constants are for float32, not float16.
r~
- Re: [Qemu-devel] [RFC PATCH 11/30] target/arm: implement half-precision F(MIN|MAX)(V|NMV), (continued)
- [Qemu-devel] [RFC PATCH 17/30] target/arm/translate-a64.c: add FP16 FMULX, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 26/30] tests/test-softfloat: add a simple test framework, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 22/30] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 29/30] tests/test-softfloat: add f16_to_int16 conversion test, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 13/30] target/arm/translate-a64.c: AdvSIMD scalar 3 Same FP16 initial decode, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 23/30] softfloat: add float16_rem and float16_muladd (!CHECK), Alex Bennée, 2017/10/13
- Re: [Qemu-devel] [RFC PATCH 23/30] softfloat: add float16_rem and float16_muladd (!CHECK),
Richard Henderson <=
- [Qemu-devel] [RFC PATCH 18/30] target/arm/translate-a64.c: add AdvSIMD scalar two-reg misc skeleton, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 20/30] softfloat: half-precision compare functions, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 25/30] softfloat: float16_round_to_int, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 27/30] target/arm/translate-a64.c: add FP16 FRINTP to 2 reg misc, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 30/30] target/arm/translate-a64.c: add FP16 FCVTPS to 2 reg misc, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 28/30] softfloat: float16_to_int16 conversion, Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 21/30] target/arm/translate-a64: add FP16 2-reg misc compare (zero), Alex Bennée, 2017/10/13
- [Qemu-devel] [RFC PATCH 24/30] disas_simd_indexed: support half-precision operations, Alex Bennée, 2017/10/13