[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 19/51] tcg: Remove TCGV_EQUAL*
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 19/51] tcg: Remove TCGV_EQUAL* |
Date: |
Wed, 25 Oct 2017 11:35:03 +0200 |
When we used structures for TCGv_*, we needed a macro in order to
perform a comparison. Now that we use pointers, this is just clutter.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Emilio G. Cota <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/tcg-op.h | 6 ++----
tcg/tcg.h | 4 ----
target/cris/translate.c | 6 +++---
target/i386/translate.c | 6 +++---
target/m68k/translate.c | 2 +-
target/ppc/translate.c | 4 ++--
6 files changed, 11 insertions(+), 17 deletions(-)
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index ab2f3c6cee..3129159907 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -328,7 +328,7 @@ static inline void tcg_gen_discard_i32(TCGv_i32 arg)
static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
{
- if (!TCGV_EQUAL_I32(ret, arg)) {
+ if (ret != arg) {
tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
}
}
@@ -522,7 +522,7 @@ static inline void tcg_gen_discard_i64(TCGv_i64 arg)
static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
{
- if (!TCGV_EQUAL_I64(ret, arg)) {
+ if (ret != arg) {
tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
}
}
@@ -809,7 +809,6 @@ void tcg_gen_lookup_and_goto_ptr(void);
#define tcg_temp_free tcg_temp_free_i32
#define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
#define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I32(x)
-#define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32
#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32
#else
@@ -820,7 +819,6 @@ void tcg_gen_lookup_and_goto_ptr(void);
#define tcg_temp_free tcg_temp_free_i64
#define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
#define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I64(x)
-#define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64
#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64
#endif
diff --git a/tcg/tcg.h b/tcg/tcg.h
index b7fac0db8a..8f692bc6cf 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -428,10 +428,6 @@ typedef TCGv_ptr TCGv_env;
#error Unhandled TARGET_LONG_BITS value
#endif
-#define TCGV_EQUAL_I32(a, b) ((a) == (b))
-#define TCGV_EQUAL_I64(a, b) ((a) == (b))
-#define TCGV_EQUAL_PTR(a, b) ((a) == (b))
-
/* Dummy definition to avoid compiler warnings. */
#define TCGV_UNUSED_I32(x) (x = (TCGv_i32)-1)
#define TCGV_UNUSED_I64(x) (x = (TCGv_i64)-1)
diff --git a/target/cris/translate.c b/target/cris/translate.c
index 38a999e6f1..55a9202777 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -839,7 +839,7 @@ static void cris_alu(DisasContext *dc, int op,
}
tcg_gen_or_tl(d, d, tmp);
}
- if (!TCGV_EQUAL(tmp, d)) {
+ if (tmp != d) {
tcg_temp_free(tmp);
}
}
@@ -1162,7 +1162,7 @@ static inline void t_gen_sext(TCGv d, TCGv s, int size)
tcg_gen_ext8s_i32(d, s);
} else if (size == 2) {
tcg_gen_ext16s_i32(d, s);
- } else if (!TCGV_EQUAL(d, s)) {
+ } else {
tcg_gen_mov_tl(d, s);
}
}
@@ -1173,7 +1173,7 @@ static inline void t_gen_zext(TCGv d, TCGv s, int size)
tcg_gen_ext8u_i32(d, s);
} else if (size == 2) {
tcg_gen_ext16u_i32(d, s);
- } else if (!TCGV_EQUAL(d, s)) {
+ } else {
tcg_gen_mov_tl(d, s);
}
}
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 5f24a2de3c..d6697f721c 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -742,7 +742,7 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv
reg)
size = s->cc_op - CC_OP_SUBB;
t1 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false);
/* If no temporary was used, be careful not to alias t1 and t0. */
- t0 = TCGV_EQUAL(t1, cpu_cc_src) ? cpu_tmp0 : reg;
+ t0 = t1 == cpu_cc_src ? cpu_tmp0 : reg;
tcg_gen_mov_tl(t0, cpu_cc_srcT);
gen_extu(size, t0);
goto add_sub;
@@ -951,7 +951,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b,
TCGv reg)
break;
case JCC_L:
gen_compute_eflags(s);
- if (TCGV_EQUAL(reg, cpu_cc_src)) {
+ if (reg == cpu_cc_src) {
reg = cpu_tmp0;
}
tcg_gen_shri_tl(reg, cpu_cc_src, 4); /* CC_O -> CC_S */
@@ -962,7 +962,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b,
TCGv reg)
default:
case JCC_LE:
gen_compute_eflags(s);
- if (TCGV_EQUAL(reg, cpu_cc_src)) {
+ if (reg == cpu_cc_src) {
reg = cpu_tmp0;
}
tcg_gen_shri_tl(reg, cpu_cc_src, 4); /* CC_O -> CC_S */
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index d738f32f9c..63b1552669 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -58,7 +58,7 @@ static TCGv_i64 cpu_macc[4];
#define QREG_SP get_areg(s, 7)
static TCGv NULL_QREG;
-#define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG))
+#define IS_NULL_QREG(t) (t == NULL_QREG)
/* Used to distinguish stores from bad addressing modes. */
static TCGv store_dummy;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index a81ff69d75..616cf8f50e 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -902,7 +902,7 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv
ret, TCGv arg1,
gen_set_Rc0(ctx, t0);
}
- if (!TCGV_EQUAL(t0, ret)) {
+ if (t0 != ret) {
tcg_gen_mov_tl(ret, t0);
tcg_temp_free(t0);
}
@@ -1438,7 +1438,7 @@ static inline void gen_op_arith_subf(DisasContext *ctx,
TCGv ret, TCGv arg1,
gen_set_Rc0(ctx, t0);
}
- if (!TCGV_EQUAL(t0, ret)) {
+ if (t0 != ret) {
tcg_gen_mov_tl(ret, t0);
tcg_temp_free(t0);
}
--
2.13.6
- [Qemu-devel] [PULL 13/51] tcg: Use per-temp state data in optimize, (continued)
- [Qemu-devel] [PULL 13/51] tcg: Use per-temp state data in optimize, Richard Henderson, 2017/10/25
- [Qemu-devel] [PULL 18/51] tcg: Remove GET_TCGV_* and MAKE_TCGV_*, Richard Henderson, 2017/10/25
- [Qemu-devel] [PULL 21/51] tcg: Use offsets not indices for TCGv_*, Richard Henderson, 2017/10/25
- [Qemu-devel] [PULL 17/51] tcg: Introduce temp_tcgv_{i32,i64,ptr}, Richard Henderson, 2017/10/25
- [Qemu-devel] [PULL 24/51] tcg: Include CF_COUNT_MASK in CF_HASH_MASK, Richard Henderson, 2017/10/25
- [Qemu-devel] [PULL 16/51] tcg: Introduce tcgv_{i32, i64, ptr}_{arg, temp}, Richard Henderson, 2017/10/25
- [Qemu-devel] [PULL 23/51] tcg: Add CPUState cflags_next_tb, Richard Henderson, 2017/10/25
- [Qemu-devel] [PULL 22/51] tcg: define CF_PARALLEL and use it for TB hashing along with CF_COUNT_MASK, Richard Henderson, 2017/10/25
- [Qemu-devel] [PULL 20/51] qom: Introduce CPUClass.tcg_initialize, Richard Henderson, 2017/10/25
- [Qemu-devel] [PULL 19/51] tcg: Remove TCGV_EQUAL*,
Richard Henderson <=
- [Qemu-devel] [PULL 26/51] target/arm: check CF_PARALLEL instead of parallel_cpus, Richard Henderson, 2017/10/25
- [Qemu-devel] [PULL 27/51] target/hppa: check CF_PARALLEL instead of parallel_cpus, Richard Henderson, 2017/10/25
- [Qemu-devel] [PULL 28/51] target/i386: check CF_PARALLEL instead of parallel_cpus, Richard Henderson, 2017/10/25
- [Qemu-devel] [PULL 31/51] target/sh4: check CF_PARALLEL instead of parallel_cpus, Richard Henderson, 2017/10/25
- [Qemu-devel] [PULL 25/51] tcg: convert tb->cflags reads to tb_cflags(tb), Richard Henderson, 2017/10/25
- [Qemu-devel] [PULL 29/51] target/m68k: check CF_PARALLEL instead of parallel_cpus, Richard Henderson, 2017/10/25
- [Qemu-devel] [PULL 33/51] tcg: check CF_PARALLEL instead of parallel_cpus, Richard Henderson, 2017/10/25
- [Qemu-devel] [PULL 30/51] target/s390x: check CF_PARALLEL instead of parallel_cpus, Richard Henderson, 2017/10/25
- [Qemu-devel] [PULL 34/51] cpu-exec: lookup/generate TB outside exclusive region during step_atomic, Richard Henderson, 2017/10/25
- [Qemu-devel] [PULL 32/51] target/sparc: check CF_PARALLEL instead of parallel_cpus, Richard Henderson, 2017/10/25