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Re: [Qemu-devel] [PATCH 0/2] Add 8-byte wide AMD flash support, partial

From: Nawrocki, Michael
Subject: Re: [Qemu-devel] [PATCH 0/2] Add 8-byte wide AMD flash support, partial interleaving
Date: Wed, 1 Nov 2017 15:01:25 +0000

On 10/31/17, 13:00, "Peter Maydell" <address@hidden> wrote:

    On 31 October 2017 at 15:44, Mike Nawrocki
    <address@hidden> wrote:
    > This patch set does a few things. First, it switches the AMD CFI flash 
    > operations from the old MMIO API to the new one. Second, it enables 8-byte
    > wide flash arrays. Finally, it supports rudimentary interleaving of 
    > flash "chips". It is expected that commands will be sent to all "chips"
    > simultaneously. See the example in the second patch for more details. This
    > behavior is used by drivers for the PPMC7400 PowerPC evaluation board.
    I'm confused by the interleaving part. Can you explain how this
    differs from the interleaving we already support in pflash_cfi01.c
    via setting width, device-width and max-device-width ? (see the comment
    in the pflash_cfi01_properties[] array about how those settings
    interact). If it is the same thing, we should really implement it
    in the same way for both kinds of flash device.
    -- PMM

Looking through pflash_cfi01.c, it looks essentially the same, though my code 
doesn’t represent max_device_width. The interleaving in pflash_cfi01.c is more 
robust than what I implemented. Should I revert the changes to the 
pflash_cfi02_register prototype and mirror the qdev property implementation 
pflash_cfi01 uses? This would drastically reduce the number of files affected.


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