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[Qemu-devel] [Bug 1353346] Re: ARMv7-M software-triggered interrupts-- u

From: Peter Maydell
Subject: [Qemu-devel] [Bug 1353346] Re: ARMv7-M software-triggered interrupts-- unexpected behaviour
Date: Fri, 03 Nov 2017 16:29:11 -0000

This bug was fixed in QEMU 2.9 as part of the rewrite of M profile
exception handling.

** Changed in: qemu
       Status: New => Fix Released

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  ARMv7-M software-triggered interrupts-- unexpected behaviour

Status in QEMU:
  Fix Released

Bug description:
  The handling of the NVIC "Software Triggered Interrupt Register" in
  qemu-2.1.0/hw/intc/armv7m_nvic.c:375 isn't quite right.  As things
  stand, writing a zero to the STIR ends up transferring control to
  vector table entry zero, which, on ARMv7-M, holds the reset value of
  the stack pointer.  That's what I see with lm3s811evb emulation, and
  that's not what happens on my STM NUCLEO-F103RB board (Cortex-M3).

  Seems like an oversight-- the handler probably wants
  armv7m_nvic_set_pending(), not gic_set_pending_private(), and the IRQ
  number needs 16 added onto it to get the exception number for the

  ARM DUI 0552A (Cortex-M3 Devices: Generic User's Guide), p. 134:
    "Interrupt ID of the interrupt to trigger, in the range 0-239. For example, 
a value of 0x03 specifies interrupt IRQ3."


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