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Re: [Qemu-devel] [RFC PATCH v2 01/21] ppc/xive: introduce a skeleton for
Cédric Le Goater
Re: [Qemu-devel] [RFC PATCH v2 01/21] ppc/xive: introduce a skeleton for the sPAPR XIVE interrupt controller
Thu, 16 Nov 2017 17:48:56 +0100
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On 09/26/2017 11:45 AM, Benjamin Herrenschmidt wrote:
> On Tue, 2017-09-26 at 13:54 +1000, David Gibson wrote:
>>>> Which ones? My impression was that there needed to be at least #cpus
>>>> * #priority-levels EQs, but there could be more than that,
>>> euh no, not in spapr mode at least. There are 8 queues per cpu.
> There's a HW feature of XIVE in DD2.x that I will start exploiting soon
> that sacrifices a queue btw, keep that in mind.
> We should probably only expose 0...6 to guests, not 0...7.
yes. This is achieved using the "ibm,plat-res-int-priorities" property
of the device tree.
I don't think we also need to check these priority ranges when allocating
the EQs. We can just allocate them all (8 priorities) and let the hcalls
do the checks. They should return H_P3 or H_P4 if the prio is invalid.