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Re: [Qemu-devel] [qemu-s390x] [PATCH v3 1/7] s390x/pci: factor out endia

From: Yi Min Zhao
Subject: Re: [Qemu-devel] [qemu-s390x] [PATCH v3 1/7] s390x/pci: factor out endianess conversion
Date: Mon, 27 Nov 2017 14:31:36 +0800
User-agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.13; rv:52.0) Gecko/20100101 Thunderbird/52.4.0

在 2017/11/25 下午9:49, Pierre Morel 写道:
On 24/11/2017 07:19, Yi Min Zhao wrote:

在 2017/11/23 下午8:18, Thomas Huth 写道:
On 23.11.2017 13:07, Yi Min Zhao wrote:

在 2017/11/23 下午6:33, Cornelia Huck 写道:
On Thu, 23 Nov 2017 11:25:10 +0100
Thomas Huth <address@hidden> wrote:

On 23.11.2017 11:08, Cornelia Huck wrote:
On Thu, 23 Nov 2017 11:01:23 +0100
Thomas Huth <address@hidden> wrote:
On 23.11.2017 10:49, Cornelia Huck wrote:
On Thu, 23 Nov 2017 09:48:41 +0100
Thomas Huth <address@hidden> wrote:
On 22.11.2017 23:05, Pierre Morel wrote:
+ * Swap data contained in s390x big endian registers to little
+ * PCI bars.
+ *
+ * @ptr: a pointer to a uint64_t data field
+ * @len: the length of the valid data, must be 1,2,4 or 8
+ */
+static int zpci_endian_swap(uint64_t *ptr, uint8_t len)
+    uint64_t data = *ptr;
+    switch (len) {
+    case 1:
+        break;
+    case 2:
+        data = bswap16(data);
+        break;
+    case 4:
+        data = bswap32(data);
+        break;
+    case 8:
+        data = bswap64(data);
+        break;
+    default:
+        return -EINVAL;
+    }
+    *ptr = data;
+    return 0;
While you're at it, I think that should rather be leXX_to_cpu()
of bswapXX() here,
I don't think that's correct, as this is supposed to swap BE
to LE PCI bars.
Yes, but for the CPU emulation, the registers are stored in the host's endianness in the CPUS390XState structure. Or why do we byte-swap them
again with cpu_to_be64() during s390_store_status(), for example?
Gah, endian conversion is eating my brain...

So, is the content we get BE or not? I thought in our last discussion
we came to the conclusion that it is.
data is read from / written to env->regs[r1], so this is host endian, as
far as I know. PCI is little endian, so using le32_to_cpu() /
cpu_to_le32() should IMHO be the right way to go here.

By the way, if we want to use both, cpu_to_le and le_to_cpu, depending on whether we read from or write to PCI, we should maybe *not* put this
code into a separate function?
Yes, if your assessment is correct, we need two functions (I think this
conversion is used in other places in later patches as well). Or are
there mechanisms for that already available?
I have a question, is the data in cpu->regs the guest's endianess?
As far as I know, it's host endianness, so on x86 with TCG emulation,
it's little endian.

In our case, the guest is S390. Although the arch is big-endian, the
data in
pcilg/stg instructions is little-endian.
PCI memory is always little endian, right.

Another question, does 'cpu' in cpu_to_le**() or le**_to_cpu() mean the
host endianess?
Yes, the "cpu" in cpu_to_le or le_to_cpu means the host, indeed. It's
confusing :-/

If the answers to upper two questions are yes, we actually need handle
two cases.
1) For pcilg, we need to translate the data to little-endian, thus
2) For pcistg, we need to translate the data to host endianess, thus
I think we've got to byte-swap if the host is big endian (s390x), but
not if the host is little endian (x86 with TCG).

Here is my comprehension of this funny swapping:

- TCG for a BE guest and a le host swap bytes because if we do (register & 0x01) in the zPCI interception code it must work what ever the endianess is.

- Guest always write data Little Endian because it think it writes to PCI.

- Kernel standard PCI code needs to swap endianness for a BE host but not for a le host.

So it follows:

Z Guest writes data BE in its register and swap its data to le before issuing zPCI
The data in register has been already le. For any zPCI instruction accessing
PCI data, the endianess is little-endian. Although s390 is be, its PCI instructions
follow PCI Spec (byte ordering is le).

In kernel, s390 pci code swaps the data to le before it really issues pcistg.

QEMU intercepts, receives the data from the register and store it
    -> Native: it stores as is: -> le
I think you talked about PCI stg (storing data to PCI device).
The data from the register is le. But we swapped it back to be
because qemu in s390 is be. Then any pci_config write would
transfer data from be to le finally. The process is:
1) data from register : le (because the data in pcistg is in le)
2) pcistg intercept handler in qemu : le->be
3) pci->config_write : be->le
    -> TCG: it stores swapping data -> BE
For this case, we only talk about the case that the host is le.
As my understanding, the data in the register should be in
the byte ordering which the guest is.

So, for s390 guest, the data in pcistg is le. Then pcistg intercept
handler swaps the data from le to be, thus the final callback
would write the data with the wrong byte ordering to PCI device
because the host is le and cpu_to_le32() would not swaps the data.

QEMU-PCI swaps the bytes always
    -> Native : data is now BE
    -> TCG: data is now le
Why is the data le under TCG? Isn't the data stored in register
the same as the guest's endianess?

QEMU send the data to the PCI card
    -> Native, it goes through kernel which swap BE ->le
    -> TCG: data is directly written to PCI memory: -> le

So for my view, we must always swap data. if we want it le at the end

It comes because
1) guest and host kernels both make and translation BE->le
   the QEMU PCI needs to swap back the data before sending to the host

2) TCG swap the bytes, i.e. le->BE on saving registers
   the QEMU PCI writes directly to the memory then it needs to swap to
   back to le

I may have miss something or misunderstood something else so : Is it right?



Thanks for your replies! We will send the new version ASAP to udpate this patch.


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