[Qemu-devel] [PATCH v2] target/arm: Fix stlxp for aarch64_be

[Michael Weiser]

ldxp loads two consecutive doublewords from memory regardless of CPU
endianness. On store, stlxp currently assumes to work with a 128bit
value and consequently switches order in big-endian mode. With this
change it packs the doublewords in reverse order in anticipation of the
128bit big-endian store operation interposing them so they end up in
memory in the right order. This makes it work for both MTTCG and !MTTCG.
It effectively implements the ARM ARM STLXP operation pseudo-code:

data = if BigEndian() then el1:el2 else el2:el1;

With this change an aarch64_be Linux 4.14.4 kernel succeeds to boot up
in system emulation mode.

Signed-off-by: Michael Weiser <address@hidden>
---
 target/arm/helper-a64.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

v2:
- make it work for MTTCG as well by catering to the 128bit expectation

diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index b84ebcae6e..3adb88db6a 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -506,8 +506,10 @@ static uint64_t do_paired_cmpxchg64_be(CPUARMState *env, 
uint64_t addr,
     Int128 oldv, cmpv, newv;
     bool success;
 
-    cmpv = int128_make128(env->exclusive_val, env->exclusive_high);
-    newv = int128_make128(new_lo, new_hi);
+    /* high and low need to be switched here because this is not actually a
+     * 128bit store but two doulbewords stored consecutively */
+    cmpv = int128_make128(env->exclusive_high, env->exclusive_val);
+    newv = int128_make128(new_hi, new_lo);
 
     if (parallel) {
 #ifndef CONFIG_ATOMIC128
-- 
2.15.1