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Re: [Qemu-devel] [PATCH v1 04/21] RISC-V Disassembler
From: |
Michael Clark |
Subject: |
Re: [Qemu-devel] [PATCH v1 04/21] RISC-V Disassembler |
Date: |
Thu, 4 Jan 2018 11:12:04 +1300 |
On Wed, Jan 3, 2018 at 6:30 PM, Richard Henderson <
address@hidden> wrote:
> On 01/02/2018 04:44 PM, Michael Clark wrote:
> > +static const char *rv_ireg_name_sym[] = {
> > + "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2",
> > + "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5",
> > + "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7",
> > + "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6",
> > + NULL
> > +};
>
> static const char * const
>
OK.
> But maybe even better as
>
> static const char rv_ireg_name_sym[32][4]
>
Got it, but it would need to be [32][5] to make room for the NULL
terminator on zero.
> and without the useless NULL.
>
Yes. they are redundant.
> Otherwise,
>
> Reviewed-by: Richard Henderson <address@hidden>
>
Thanks.
These changes will be in the next spin of the patchset.
- Re: [Qemu-devel] [PATCH v1 05/21] RISC-V CPU Helpers, (continued)
Re: [Qemu-devel] [PATCH v1 05/21] RISC-V CPU Helpers, Christoph Hellwig, 2018/01/08
[Qemu-devel] [PATCH v1 07/21] RISC-V GDB Stub, Michael Clark, 2018/01/02
[Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support, Michael Clark, 2018/01/02
[Qemu-devel] [PATCH v1 04/21] RISC-V Disassembler, Michael Clark, 2018/01/02
[Qemu-devel] [PATCH v1 09/21] RISC-V Physical Memory Protection, Michael Clark, 2018/01/02
[Qemu-devel] [PATCH v1 12/21] RISC-V HART Array, Michael Clark, 2018/01/02
[Qemu-devel] [PATCH v1 08/21] RISC-V TCG Code Generation, Michael Clark, 2018/01/02
[Qemu-devel] [PATCH v1 10/21] RISC-V Linux User Emulation, Michael Clark, 2018/01/02