Re: [Qemu-devel] [PATCH v1 19/21] SiFive Freedom E300 RISC-V Machine

[Antony Pavlov]

On Wed,  3 Jan 2018 13:44:23 +1300
Michael Clark <address@hidden> wrote:

> This provides a RISC-V Board compatible with the the SiFive E300 SDK.
> The following machine is implemented:
> 
> - 'sifive_e300'; CLINT, PLIC, UART, AON, GPIO, QSPI, PWM
> 

...

> diff --git a/include/hw/riscv/sifive_e300.h b/include/hw/riscv/sifive_e300.h
> new file mode 100644
> index 0000000..453c43b
> --- /dev/null
> +++ b/include/hw/riscv/sifive_e300.h
> @@ -0,0 +1,79 @@
> +/*
> + * SiFive E300 series machine interface
> + *
> + * Copyright (c) 2017 SiFive, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a 
> copy
> + * of this software and associated documentation files (the "Software"), to 
> deal
> + * in the Software without restriction, including without limitation the 
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
> FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#ifndef HW_SIFIVE_E300_H
> +#define HW_SIFIVE_E300_H
> +
> +#define TYPE_SIFIVE_E300 "riscv.sifive.e300"
> +
> +#define SIFIVE_E300(obj) \
> +    OBJECT_CHECK(SiFiveE300State, (obj), TYPE_SIFIVE_E300)
> +
> +typedef struct SiFiveE300State {
> +    /*< private >*/
> +    SysBusDevice parent_obj;
> +
> +    /*< public >*/
> +    RISCVHartArrayState soc;

I suppose that name 'soc' is misleading because it contain only CPU 
core-related information
but it does not contain any SoC-related information.

> +    DeviceState *plic;
> +} SiFiveE300State;
> +



-- 
Best regards,
  Antony Pavlov