[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 21/22] target/ppc: add support for POWER9 HILE
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 21/22] target/ppc: add support for POWER9 HILE |
Date: |
Wed, 17 Jan 2018 13:25:24 +1100 |
From: Cédric Le Goater <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/cpu.h | 1 +
target/ppc/excp_helper.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index dc6820c5eb..14aaa87fe8 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2012,6 +2012,7 @@ void ppc_compat_add_property(Object *obj, const char
*name,
#define HID0_DOZE (1 << 23) /* pre-2.06 */
#define HID0_NAP (1 << 22) /* pre-2.06 */
#define HID0_HILE PPC_BIT(19) /* POWER8 */
+#define HID0_POWER9_HILE PPC_BIT(4)
/*****************************************************************************/
/* PowerPC Instructions types definitions */
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 37d2410726..4e548a4487 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -654,7 +654,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
}
} else if (excp_model == POWERPC_EXCP_POWER8) {
if (new_msr & MSR_HVB) {
- if (env->spr[SPR_HID0] & HID0_HILE) {
+ if (env->spr[SPR_HID0] & (HID0_HILE | HID0_POWER9_HILE)) {
new_msr |= (target_ulong)1 << MSR_LE;
}
} else if (env->spr[SPR_LPCR] & LPCR_ILE) {
--
2.14.3
- [Qemu-devel] [PULL 15/22] tests/boot-serial-test: fix powernv support, (continued)
- [Qemu-devel] [PULL 15/22] tests/boot-serial-test: fix powernv support, David Gibson, 2018/01/16
- [Qemu-devel] [PULL 17/22] ppc/pnv: change core mask for POWER9, David Gibson, 2018/01/16
- [Qemu-devel] [PULL 13/22] spapr: Adjust default VSMT value for better migration compatibility, David Gibson, 2018/01/16
- [Qemu-devel] [PULL 18/22] ppc/pnv: introduce pnv*_is_power9() helpers, David Gibson, 2018/01/16
- [Qemu-devel] [PULL 16/22] ppc/pnv: use POWER9 DD2 processor, David Gibson, 2018/01/16
- [Qemu-devel] [PULL 22/22] target-ppc: Fix booke206 tlbwe TLB instruction, David Gibson, 2018/01/16
- [Qemu-devel] [PULL 07/22] spapr: Handle Decimal Floating Point (DFP) as an optional capability, David Gibson, 2018/01/16
- [Qemu-devel] [PULL 11/22] target/ppc: Clarify compat mode max_threads value, David Gibson, 2018/01/16
- [Qemu-devel] [PULL 09/22] spapr: Remove unnecessary 'options' field from sPAPRCapabilityInfo, David Gibson, 2018/01/16
- [Qemu-devel] [PULL 03/22] spapr: Treat Hardware Transactional Memory (HTM) as an optional capability, David Gibson, 2018/01/16
- [Qemu-devel] [PULL 21/22] target/ppc: add support for POWER9 HILE,
David Gibson <=
- [Qemu-devel] [PULL 20/22] ppc/pnv: change initrd address, David Gibson, 2018/01/16
- [Qemu-devel] [PULL 12/22] spapr: Allow some cases where we can't set VSMT mode in the kernel, David Gibson, 2018/01/16
- [Qemu-devel] [PULL 08/22] hw/ppc/spapr_caps: Rework spapr_caps to use uint8 internal representation, David Gibson, 2018/01/16
- [Qemu-devel] [PULL 19/22] ppc/pnv: fix XSCOM core addressing on POWER9, David Gibson, 2018/01/16
- Re: [Qemu-devel] [PULL 00/22] ppc-for-2.12 queue 20180117, Peter Maydell, 2018/01/18