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[Qemu-devel] [PATCH 4/7] hw/mips_int: hold BQL for all interrupt request
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH 4/7] hw/mips_int: hold BQL for all interrupt requests |
Date: |
Fri, 19 Jan 2018 16:56:28 +0100 |
From: Miodrag Dinic <address@hidden>
Make sure BQL is held for all interrupt requests.
For MTTCG-enabled configurations, handling soft and hard interrupts
between vCPUs must be properly locked. By acquiring BQL, make sure
all paths triggering an IRQ are synchronized.
Signed-off-by: Miodrag Dinic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
hw/mips/mips_int.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c
index 48192d2..5ddeb15 100644
--- a/hw/mips/mips_int.c
+++ b/hw/mips/mips_int.c
@@ -21,6 +21,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/main-loop.h"
#include "hw/hw.h"
#include "hw/mips/cpudevs.h"
#include "cpu.h"
@@ -32,10 +33,17 @@ static void cpu_mips_irq_request(void *opaque, int irq, int
level)
MIPSCPU *cpu = opaque;
CPUMIPSState *env = &cpu->env;
CPUState *cs = CPU(cpu);
+ bool locked = false;
if (irq < 0 || irq > 7)
return;
+ /* Make sure locking works even if BQL is already held by the caller */
+ if (!qemu_mutex_iothread_locked()) {
+ locked = true;
+ qemu_mutex_lock_iothread();
+ }
+
if (level) {
env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
@@ -56,6 +64,10 @@ static void cpu_mips_irq_request(void *opaque, int irq, int
level)
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
+
+ if (locked) {
+ qemu_mutex_unlock_iothread();
+ }
}
void cpu_mips_irq_init_cpu(MIPSCPU *cpu)
--
2.7.4
- [Qemu-devel] [PATCH 0/7] target-mips: support MTTCG feature, Aleksandar Markovic, 2018/01/19
- [Qemu-devel] [PATCH 4/7] hw/mips_int: hold BQL for all interrupt requests,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH 6/7] hw/mips_cpc: kick a VP when putting it into Run state, Aleksandar Markovic, 2018/01/19
- [Qemu-devel] [PATCH 5/7] target/mips: hold BQL in mips_vpe_wake(), Aleksandar Markovic, 2018/01/19
- [Qemu-devel] [PATCH 1/7] target/mips: compare virtual addresses in LL/SC sequence, Aleksandar Markovic, 2018/01/19
- [Qemu-devel] [PATCH 2/7] target/mips: reimplement SC instruction and use cmpxchg, Aleksandar Markovic, 2018/01/19
- [Qemu-devel] [PATCH 7/7] target/mips: introduce MTTCG-enabled builds, Aleksandar Markovic, 2018/01/19
- [Qemu-devel] [PATCH 3/7] Revert "target/mips: hold BQL for timer interrupts", Aleksandar Markovic, 2018/01/19