Re: [Qemu-devel] [PATCH v3 21/21] RISC-V Build Infrastructure

[Michael Clark]

On Fri, Jan 12, 2018 at 7:43 AM, Michael Clark <address@hidden> wrote:

>
>
> On Fri, Jan 12, 2018 at 3:05 AM, Eric Blake <address@hidden> wrote:
>
>> On 01/10/2018 08:22 PM, Michael Clark wrote:
>> > This adds RISC-V into the build system enabling the following targets:
>> >
>> > - riscv32-softmmu
>> > - riscv64-softmmu
>> > - riscv32-linux-user
>> > - riscv64-linux-user
>> >
>> > This adds defaults configs for RISC-V, enables the build for the RISC-V
>> > CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh'
>> > script is updated to add the RISC-V ELF magic.
>> >
>> > +++ b/qapi-schema.json
>> > @@ -413,7 +413,7 @@
>> >  # Since: 2.6
>> >  ##
>> >  { 'enum': 'CpuInfoArch',
>> > -  'data': ['x86', 'sparc', 'ppc', 'mips', 'tricore', 'other' ] }
>> > +  'data': ['x86', 'sparc', 'ppc', 'mips', 'tricore', 'riscv', 'other'
>> ] }
>>
>> Still missing documentation that riscv was added in 2.12 (see my
>> comments on v1).
>
>
> My apologies. I had a look at QKeyCode and it was not clear to me how to
> specify since on an enum value vs a field.
>
> --- a/qapi-schema.json
> +++ b/qapi-schema.json
> @@ -411,6 +411,9 @@
>  # @query-cpus.
>
> why is this @query-cpus and not @CpuInfoArch: as is the case for @QKeyCode?
>
>  #
>  # Since: 2.6
> +#
> +# @riscv: since 2.12
> +#
>  ##
>  { 'enum': 'CpuInfoArch',
>    'data': ['x86', 'sparc', 'ppc', 'mips', 'tricore', 'riscv', 'other' ] }
>
>  Is this correct?
>

I figured this out. The enum value since needs to come before the main
since otherwise we get qapi-schema.json:415:1: '@riscv:' can't follow
'Since' section.

This way around appears to work:

diff --git a/qapi-schema.json b/qapi-schema.json
index 42d91f3..79a2f62 100644
--- a/qapi-schema.json
+++ b/qapi-schema.json
@@ -410,6 +410,8 @@
 # An enumeration of cpu types that enable additional information during
 # @query-cpus.
 #
+# @riscv: since 2.12
+#
 # Since: 2.6
 ##
 { 'enum': 'CpuInfoArch',



> > --- /dev/null
>> > +++ b/target/riscv/trace-events
>> > @@ -0,0 +1 @@
>> > +# See docs/devel/tracing.txt for syntax documentation.
>> >
>>
>> Do we really need this file if you don't have any traces yet?
>>
>
> I'll remove the file or add some tracing in the next spin.
>

I tried removing target/riscv/trace-events however, it broke the build so I
am going to leave it there for the next spin...