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[Qemu-devel] [PATCH 7/8] target/arm: Implement writing to CONTROL_NS for
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 7/8] target/arm: Implement writing to CONTROL_NS for v8M |
Date: |
Mon, 5 Feb 2018 10:57:19 +0000 |
In commit 50f11062d4c896 we added support for MSR/MRS access
to the NS banked special registers, but we forgot to implement
the support for writing to CONTROL_NS. Correct the omission.
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 3332565101..abb4d94a7f 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10388,6 +10388,16 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t
maskreg, uint32_t val)
}
env->v7m.faultmask[M_REG_NS] = val & 1;
return;
+ case 0x94: /* CONTROL_NS */
+ if (!env->v7m.secure) {
+ return;
+ }
+ write_v7m_control_spsel_for_secstate(env,
+ val &
R_V7M_CONTROL_SPSEL_MASK,
+ M_REG_NS);
+ env->v7m.control[M_REG_NS] &= ~R_V7M_CONTROL_NPRIV_MASK;
+ env->v7m.control[M_REG_NS] |= val & R_V7M_CONTROL_NPRIV_MASK;
+ return;
case 0x98: /* SP_NS */
{
/* This gives the non-secure SP selected based on whether we're
--
2.16.1
- [Qemu-devel] [PATCH 0/8] v8m: minor missing regs and bugfixes, Peter Maydell, 2018/02/05
- [Qemu-devel] [PATCH 7/8] target/arm: Implement writing to CONTROL_NS for v8M,
Peter Maydell <=
- [Qemu-devel] [PATCH 6/8] hw/intc/armv7m_nvic: Implement SCR, Peter Maydell, 2018/02/05
- [Qemu-devel] [PATCH 5/8] hw/intc/armv7m_nvic: Implement cache ID registers, Peter Maydell, 2018/02/05
- [Qemu-devel] [PATCH 8/8] hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions, Peter Maydell, 2018/02/05
- [Qemu-devel] [PATCH 3/8] hw/intc/armv7m_nvic: Implement M profile cache maintenance ops, Peter Maydell, 2018/02/05
- [Qemu-devel] [PATCH 2/8] hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling, Peter Maydell, 2018/02/05
- [Qemu-devel] [PATCH 4/8] hw/intc/armv7m_nvic: Implement v8M CPPWR register, Peter Maydell, 2018/02/05