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Re: [Qemu-devel] [PATCH v6 5/5] target/arm: enable user-mode SHA-3, SM3,
From: |
Ard Biesheuvel |
Subject: |
Re: [Qemu-devel] [PATCH v6 5/5] target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support |
Date: |
Wed, 7 Feb 2018 12:00:45 +0000 |
On 7 February 2018 at 11:57, Laurent Desnogues
<address@hidden> wrote:
> On Wed, Feb 7, 2018 at 12:53 PM, Ard Biesheuvel
> <address@hidden> wrote:
>> On 7 February 2018 at 11:49, Alex Bennée <address@hidden> wrote:
>>>
>>> Ard Biesheuvel <address@hidden> writes:
>>>
>>>> Add support for the new ARMv8.2 SHA-3, SM3, SM4 and SHA-512 instructions to
>>>> AArch64 user mode emulation.
>>>
>>> Are you aware of any processors with ARMv8.2 available yet? It might be
>>> nice to have a more recent model for system emulation and the pieces
>>> seems to be coming together.
>>>
>>
>> I think Peter's idea was to have so kind of 'max' cpu type that
>> enables all optional extensions in system emulation mode.
>> AFAIK none of the Cortex-Axx cores that are public are available with
>> these crypto features.
>
> Cortex-A75 is ARMv8.2. It should be available in devices this year.
>
Yeah, but according to the docs on infocenter.arm.com, it does not
implement the newer crypto instructions.
- [Qemu-devel] [PATCH v6 0/5] target-arm: add SHA-3, SM3 and SHA512 instruction support, Ard Biesheuvel, 2018/02/07
- [Qemu-devel] [PATCH v6 3/5] target/arm: implement SM3 instructions, Ard Biesheuvel, 2018/02/07
- [Qemu-devel] [PATCH v6 4/5] target/arm: implement SM4 instructions, Ard Biesheuvel, 2018/02/07
- [Qemu-devel] [PATCH v6 1/5] target/arm: implement SHA-512 instructions, Ard Biesheuvel, 2018/02/07
- [Qemu-devel] [PATCH v6 2/5] target/arm: implement SHA-3 instructions, Ard Biesheuvel, 2018/02/07
- [Qemu-devel] [PATCH v6 5/5] target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support, Ard Biesheuvel, 2018/02/07
- Re: [Qemu-devel] [PATCH v6 5/5] target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support, Alex Bennée, 2018/02/07
- Re: [Qemu-devel] [PATCH v6 5/5] target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support, Ard Biesheuvel, 2018/02/07
- Re: [Qemu-devel] [PATCH v6 5/5] target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support, Laurent Desnogues, 2018/02/07
- Re: [Qemu-devel] [PATCH v6 5/5] target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support,
Ard Biesheuvel <=
- Re: [Qemu-devel] [PATCH v6 5/5] target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support, Alex Bennée, 2018/02/07
Re: [Qemu-devel] [PATCH v6 0/5] target-arm: add SHA-3, SM3 and SHA512 instruction support, Peter Maydell, 2018/02/08