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[Qemu-devel] [PATCH v2 04/32] target/arm/cpu.h: update comment for half-
From: |
Alex Bennée |
Subject: |
[Qemu-devel] [PATCH v2 04/32] target/arm/cpu.h: update comment for half-precision values |
Date: |
Thu, 8 Feb 2018 17:31:29 +0000 |
Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target/arm/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index c793250186..f976969011 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -486,6 +486,7 @@ typedef struct CPUARMState {
* Qn = regs[2n+1]:regs[2n]
* Dn = regs[2n]
* Sn = regs[2n] bits 31..0
+ * Hn = regs[2n] bits 15..0 for even n, and bits 31..16 for odd n
* This corresponds to the architecturally defined mapping between
* the two execution states, and means we do not need to explicitly
* map these registers when changing states.
--
2.15.1
- [Qemu-devel] [PATCH v2 03/32] target/arm/cpu64: allow fp16 to be disabled, (continued)
- [Qemu-devel] [PATCH v2 01/32] include/exec/helper-head.h: support f16 in helper calls, Alex Bennée, 2018/02/08
- [Qemu-devel] [PATCH v2 06/32] target/arm/helper: pass explicit fpst to set_rmode, Alex Bennée, 2018/02/08
- [Qemu-devel] [PATCH v2 05/32] target/arm/cpu.h: add additional float_status flags, Alex Bennée, 2018/02/08
- [Qemu-devel] [PATCH v2 04/32] target/arm/cpu.h: update comment for half-precision values,
Alex Bennée <=
- [Qemu-devel] [PATCH v2 11/32] arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16, Alex Bennée, 2018/02/08
[Qemu-devel] [PATCH v2 08/32] arm/translate-a64: handle_3same_64 comment fix, Alex Bennée, 2018/02/08
[Qemu-devel] [PATCH v2 10/32] arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16, Alex Bennée, 2018/02/08
[Qemu-devel] [PATCH v2 09/32] arm/translate-a64: initial decode for simd_three_reg_same_fp16, Alex Bennée, 2018/02/08