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[Qemu-devel] [PULL 30/30] hw/core/generic-loader: Allow PC to be set on
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 30/30] hw/core/generic-loader: Allow PC to be set on command line |
Date: |
Fri, 9 Feb 2018 11:03:14 +0000 |
The documentation for the generic loader claims that you can
set the PC for a CPU with an option of the form
-device loader,cpu-num=0,addr=0x10000004
However if you try this QEMU complains:
cpu_num must be specified when setting a program counter
This is because we were testing against 0 rather than CPU_NONE.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
---
hw/core/generic-loader.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c
index 46012673c3..cb0e68486d 100644
--- a/hw/core/generic-loader.c
+++ b/hw/core/generic-loader.c
@@ -105,7 +105,7 @@ static void generic_loader_realize(DeviceState *dev, Error
**errp)
error_setg(errp, "data can not be specified when setting a "
"program counter");
return;
- } else if (!s->cpu_num) {
+ } else if (s->cpu_num == CPU_NONE) {
error_setg(errp, "cpu_num must be specified when setting a "
"program counter");
return;
--
2.16.1
- [Qemu-devel] [PULL 29/30] target/arm/translate.c: Fix missing 'break' for TT insns, (continued)
- [Qemu-devel] [PULL 29/30] target/arm/translate.c: Fix missing 'break' for TT insns, Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 26/30] target/arm: Add ZCR_ELx, Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 18/30] i.MX: Add code to emulate GPCv2 IP block, Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 25/30] target/arm: Add SVE to migration state, Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 03/30] target/arm: Add ignore_stackfaults argument to v7m_exception_taken(), Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 19/30] i.MX: Add i.MX7 GPT variant, Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 06/30] target/arm: Make exception vector loads honour the SAU, Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 24/30] target/arm: Add predicate registers for SVE, Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 22/30] hw/arm: Move virt's PSCI DT fixup code to arm/boot.c, Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 04/30] target/arm: Make v7M exception entry stack push check MPU, Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 30/30] hw/core/generic-loader: Allow PC to be set on command line,
Peter Maydell <=
- [Qemu-devel] [PULL 09/30] target/arm: implement SHA-3 instructions, Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 23/30] target/arm: Expand vector registers for SVE, Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 16/30] i.MX: Add code to emulate i.MX2 watchdog IP block, Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 27/30] target/arm: Add SVE state to TB->FLAGS, Peter Maydell, 2018/02/09
- [Qemu-devel] [PULL 28/30] target/arm/kvm: gic: Prevent creating userspace GICv3 with KVM, Peter Maydell, 2018/02/09
- Re: [Qemu-devel] [PULL 00/30] target-arm queue, Peter Maydell, 2018/02/09