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[Qemu-devel] [PULL 43/48] sdhci: add Spec v4.2 register definitions
From: |
Paolo Bonzini |
Subject: |
[Qemu-devel] [PULL 43/48] sdhci: add Spec v4.2 register definitions |
Date: |
Tue, 13 Feb 2018 13:00:47 +0100 |
From: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-Id: <address@hidden>
---
hw/sd/sdhci-internal.h | 9 +++++++++
hw/sd/sdhci.c | 16 +++++++++++++++-
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
index 33e8768..756ef3f 100644
--- a/hw/sd/sdhci-internal.h
+++ b/hw/sd/sdhci-internal.h
@@ -197,6 +197,10 @@ FIELD(SDHC_HOSTCTL2, V18_ENA, 3, 1); /* UHS-I
only */
FIELD(SDHC_HOSTCTL2, DRIVER_STRENGTH, 4, 2); /* UHS-I only */
FIELD(SDHC_HOSTCTL2, EXECUTE_TUNING, 6, 1); /* UHS-I only */
FIELD(SDHC_HOSTCTL2, SAMPLING_CLKSEL, 7, 1); /* UHS-I only */
+FIELD(SDHC_HOSTCTL2, UHS_II_ENA, 8, 1); /* since v4 */
+FIELD(SDHC_HOSTCTL2, ADMA2_LENGTH, 10, 1); /* since v4 */
+FIELD(SDHC_HOSTCTL2, CMD23_ENA, 11, 1); /* since v4 */
+FIELD(SDHC_HOSTCTL2, VERSION4, 12, 1); /* since v4 */
FIELD(SDHC_HOSTCTL2, ASYNC_INT, 14, 1);
FIELD(SDHC_HOSTCTL2, PRESET_ENA, 15, 1);
@@ -215,10 +219,12 @@ FIELD(SDHC_CAPAB, SUSPRESUME, 23, 1);
FIELD(SDHC_CAPAB, V33, 24, 1);
FIELD(SDHC_CAPAB, V30, 25, 1);
FIELD(SDHC_CAPAB, V18, 26, 1);
+FIELD(SDHC_CAPAB, BUS64BIT_V4, 27, 1); /* since v4.10 */
FIELD(SDHC_CAPAB, BUS64BIT, 28, 1); /* since v2 */
FIELD(SDHC_CAPAB, ASYNC_INT, 29, 1); /* since v3 */
FIELD(SDHC_CAPAB, SLOT_TYPE, 30, 2); /* since v3 */
FIELD(SDHC_CAPAB, BUS_SPEED, 32, 3); /* since v3 */
+FIELD(SDHC_CAPAB, UHS_II, 35, 8); /* since v4.20 */
FIELD(SDHC_CAPAB, DRIVER_STRENGTH, 36, 3); /* since v3 */
FIELD(SDHC_CAPAB, DRIVER_TYPE_A, 36, 1); /* since v3 */
FIELD(SDHC_CAPAB, DRIVER_TYPE_C, 37, 1); /* since v3 */
@@ -227,12 +233,15 @@ FIELD(SDHC_CAPAB, TIMER_RETUNING, 40, 4); /* since v3
*/
FIELD(SDHC_CAPAB, SDR50_TUNING, 45, 1); /* since v3 */
FIELD(SDHC_CAPAB, RETUNING_MODE, 46, 2); /* since v3 */
FIELD(SDHC_CAPAB, CLOCK_MULT, 48, 8); /* since v3 */
+FIELD(SDHC_CAPAB, ADMA3, 59, 1); /* since v4.20 */
+FIELD(SDHC_CAPAB, V18_VDD2, 60, 1); /* since v4.20 */
/* HWInit Maximum Current Capabilities Register 0x0 */
#define SDHC_MAXCURR 0x48
FIELD(SDHC_MAXCURR, V33_VDD1, 0, 8);
FIELD(SDHC_MAXCURR, V30_VDD1, 8, 8);
FIELD(SDHC_MAXCURR, V18_VDD1, 16, 8);
+FIELD(SDHC_MAXCURR, V18_VDD2, 32, 8); /* since v4.20 */
/* W Force Event Auto CMD12 Error Interrupt Register 0x0000 */
#define SDHC_FEAER 0x50
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 1a6771b..97b4a47 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -91,6 +91,20 @@ static void sdhci_check_capareg(SDHCIState *s, Error **errp)
bool y;
switch (s->sd_spec_version) {
+ case 4:
+ val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT_V4);
+ trace_sdhci_capareg("64-bit system bus (v4)", val);
+ msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT_V4, 0);
+
+ val = FIELD_EX64(s->capareg, SDHC_CAPAB, UHS_II);
+ trace_sdhci_capareg("UHS-II", val);
+ msk = FIELD_DP64(msk, SDHC_CAPAB, UHS_II, 0);
+
+ val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA3);
+ trace_sdhci_capareg("ADMA3", val);
+ msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA3, 0);
+
+ /* fallthrough */
case 3:
val = FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT);
trace_sdhci_capareg("async interrupt", val);
@@ -145,7 +159,7 @@ static void sdhci_check_capareg(SDHCIState *s, Error **errp)
msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA1, 0);
val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT);
- trace_sdhci_capareg("64-bit system bus", val);
+ trace_sdhci_capareg("64-bit system bus (v3)", val);
msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT, 0);
/* fallthrough */
--
1.8.3.1
- [Qemu-devel] [PULL 35/48] sdhci: implement CMD/DAT[] fields in the Present State register, (continued)
- [Qemu-devel] [PULL 35/48] sdhci: implement CMD/DAT[] fields in the Present State register, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 33/48] sdbus: add trace events, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 29/48] hw/arm/xilinx_zynq: fix the capabilities register to match the datasheet, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 31/48] sdhci: rename the hostctl1 register, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 40/48] hw/arm/xilinx_zynqmp: enable the UHS-I mode, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 37/48] hw/arm/bcm2835_peripherals: change maximum block size to 1kB, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 38/48] hw/arm/fsl-imx6: implement SDHCI Spec. v3, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 39/48] hw/arm/xilinx_zynqmp: fix the capabilities/spec version to match the datasheet, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 42/48] sdhci: add a check_capab_v3() qtest, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 48/48] travis: use libgcc-4.8-dev (libgcc-6-dev is not available on Ubuntu 14.04), Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 43/48] sdhci: add Spec v4.2 register definitions,
Paolo Bonzini <=
- [Qemu-devel] [PULL 47/48] memory: unify loops to sync dirty log bitmap, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 44/48] g364fb: switch to using DirtyBitmapSnapshot, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 41/48] sdhci: check Spec v3 capabilities qtest, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 46/48] memory: hide memory_region_sync_dirty_bitmap behind DirtyBitmapSnapshot, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 45/48] memory: remove memory_region_test_and_clear_dirty, Paolo Bonzini, 2018/02/13
- Re: [Qemu-devel] [PULL 00/48] Misc patches for 2018-02-13, Peter Maydell, 2018/02/13