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Re: [Qemu-devel] [PATCH v2 14/67] target/arm: Implement SVE Integer Arit
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v2 14/67] target/arm: Implement SVE Integer Arithmetic - Unary Predicated Group |
Date: |
Fri, 23 Feb 2018 17:30:54 +0000 |
On 23 February 2018 at 17:25, Richard Henderson
<address@hidden> wrote:
> On 02/23/2018 05:08 AM, Peter Maydell wrote:
>>> +# SVE unary bit operations (predicated)
>>> +# Note esz != 0 for FABS and FNEG.
>>> +CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn
>>> +CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn
>>> +CNT_zpz 00000100 .. 011 010 101 ... ..... .....
>>> @rd_pg_rn
>>> +CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn
>>> +NOT_zpz 00000100 .. 011 110 101 ... ..... .....
>>> @rd_pg_rn
>>> +FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn
>>> +FNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn
>>
>> Indentation seems to be a bit skew for the _zpz lines.
>
> There are tabs in here. I know they're not allowed for C, but this isn't.
I don't think we should have tabs in these files either for the
same reasons we don't have them in C code.
thanks
-- PMM
- Re: [Qemu-devel] [Qemu-arm] [PATCH v2 12/67] target/arm: Implement SVE bitwise shift by vector (predicated), (continued)
- [Qemu-devel] [PATCH v2 15/67] target/arm: Implement SVE Integer Multiply-Add Group, Richard Henderson, 2018/02/17
- [Qemu-devel] [PATCH v2 20/67] target/arm: Implement SVE Compute Vector Address Group, Richard Henderson, 2018/02/17
- [Qemu-devel] [PATCH v2 16/67] target/arm: Implement SVE Integer Arithmetic - Unpredicated Group, Richard Henderson, 2018/02/17
- [Qemu-devel] [PATCH v2 18/67] target/arm: Implement SVE Stack Allocation Group, Richard Henderson, 2018/02/17
- [Qemu-devel] [PATCH v2 17/67] target/arm: Implement SVE Index Generation Group, Richard Henderson, 2018/02/17