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[Qemu-devel] [PATCH v7 02/23] RISC-V ELF Machine Definition
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PATCH v7 02/23] RISC-V ELF Machine Definition |
Date: |
Tue, 27 Feb 2018 11:17:39 +1300 |
Define RISC-V ELF machine EM_RISCV 243
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
---
include/elf.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index e8a515c..8e457fc 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -112,6 +112,8 @@ typedef int64_t Elf64_Sxword;
#define EM_UNICORE32 110 /* UniCore32 */
+#define EM_RISCV 243 /* RISC-V */
+
/*
* This is an interim value that we will use until the committee comes
* up with a final number.
--
2.7.0
- [Qemu-devel] [PATCH v7 00/23] RISC-V QEMU Port Submission, Michael Clark, 2018/02/26
- [Qemu-devel] [PATCH v7 01/23] RISC-V Maintainers, Michael Clark, 2018/02/26
- [Qemu-devel] [PATCH v7 02/23] RISC-V ELF Machine Definition,
Michael Clark <=
- [Qemu-devel] [PATCH v7 03/23] RISC-V CPU Core Definition, Michael Clark, 2018/02/26
- [Qemu-devel] [PATCH v7 06/23] RISC-V FPU Support, Michael Clark, 2018/02/26
- [Qemu-devel] [PATCH v7 07/23] RISC-V GDB Stub, Michael Clark, 2018/02/26
- [Qemu-devel] [PATCH v7 05/23] RISC-V CPU Helpers, Michael Clark, 2018/02/26
- [Qemu-devel] [PATCH v7 04/23] RISC-V Disassembler, Michael Clark, 2018/02/26
- [Qemu-devel] [PATCH v7 09/23] RISC-V Physical Memory Protection, Michael Clark, 2018/02/26
- [Qemu-devel] [PATCH v7 08/23] RISC-V TCG Code Generation, Michael Clark, 2018/02/26
- [Qemu-devel] [PATCH v7 10/23] RISC-V Linux User Emulation, Michael Clark, 2018/02/26
- [Qemu-devel] [PATCH v7 11/23] Add symbol table callback interface to load_elf, Michael Clark, 2018/02/26