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[Qemu-devel] [PATCH v4 21/31] arm/translate-a64: add FP16 FNEG/FABS to s
From: |
Alex Bennée |
Subject: |
[Qemu-devel] [PATCH v4 21/31] arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16 |
Date: |
Tue, 27 Feb 2018 14:38:42 +0000 |
Neither of these operations alter the floating point status registers
so we can do a pure bitwise operation, either squashing any sign
bit (ABS) or inverting it (NEG).
Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
v3
- fixup re-base conflicts
- make both operations pure bitwise TCG
---
target/arm/translate-a64.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 6f33783a11..9f2c3682dc 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -11262,6 +11262,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext
*s, uint32_t insn)
TCGv_i32 tcg_rmode = NULL;
TCGv_ptr tcg_fpstatus = NULL;
bool need_rmode = false;
+ bool need_fpst = true;
int rmode;
if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
@@ -11380,6 +11381,10 @@ static void disas_simd_two_reg_misc_fp16(DisasContext
*s, uint32_t insn)
need_rmode = true;
rmode = FPROUNDING_ZERO;
break;
+ case 0x2f: /* FABS */
+ case 0x6f: /* FNEG */
+ need_fpst = false;
+ break;
default:
fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
g_assert_not_reached();
@@ -11403,7 +11408,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext
*s, uint32_t insn)
return;
}
- if (need_rmode) {
+ if (need_rmode || need_fpst) {
tcg_fpstatus = get_fpstatus_ptr(true);
}
@@ -11433,6 +11438,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext
*s, uint32_t insn)
case 0x7b: /* FCVTZU */
gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
break;
+ case 0x6f: /* FNEG */
+ tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
+ break;
default:
g_assert_not_reached();
}
@@ -11476,6 +11484,12 @@ static void disas_simd_two_reg_misc_fp16(DisasContext
*s, uint32_t insn)
case 0x59: /* FRINTX */
gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstatus);
break;
+ case 0x2f: /* FABS */
+ tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff);
+ break;
+ case 0x6f: /* FNEG */
+ tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
+ break;
default:
g_assert_not_reached();
}
--
2.15.1
- [Qemu-devel] [PATCH v4 13/31] arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16, (continued)
[Qemu-devel] [PATCH v4 27/31] arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16, Alex Bennée, 2018/02/27
[Qemu-devel] [PATCH v4 20/31] arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16, Alex Bennée, 2018/02/27
[Qemu-devel] [PATCH v4 26/31] arm/helper.c: re-factor rsqrte and add rsqrte_f16, Alex Bennée, 2018/02/27
[Qemu-devel] [PATCH v4 25/31] arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16, Alex Bennée, 2018/02/27
[Qemu-devel] [PATCH v4 21/31] arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16,
Alex Bennée <=
[Qemu-devel] [PATCH v4 22/31] arm/helper.c: re-factor recpe and add recepe_f16, Alex Bennée, 2018/02/27
Re: [Qemu-devel] [PATCH v4 00/31] Add ARMv8.2 half-precision functions, no-reply, 2018/02/27
Re: [Qemu-devel] [PATCH v4 00/31] Add ARMv8.2 half-precision functions, no-reply, 2018/02/27
Re: [Qemu-devel] [Qemu-arm] [PATCH v4 00/31] Add ARMv8.2 half-precision functions, Peter Maydell, 2018/02/27