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[Qemu-devel] [PULL 38/39] target/arm: Decode t32 simd 3reg and 2reg_scal
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 38/39] target/arm: Decode t32 simd 3reg and 2reg_scalar extension |
Date: |
Fri, 2 Mar 2018 11:06:39 +0000 |
From: Richard Henderson <address@hidden>
Happily, the bits are in the same places compared to a32.
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 3ad8b4031c..ba6ab7d287 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10774,7 +10774,19 @@ static void disas_thumb2_insn(DisasContext *s,
uint32_t insn)
default_exception_el(s));
break;
}
- if (((insn >> 24) & 3) == 3) {
+ if ((insn & 0xfe000a00) == 0xfc000800
+ && arm_dc_feature(s, ARM_FEATURE_V8)) {
+ /* The Thumb2 and ARM encodings are identical. */
+ if (disas_neon_insn_3same_ext(s, insn)) {
+ goto illegal_op;
+ }
+ } else if ((insn & 0xff000a00) == 0xfe000800
+ && arm_dc_feature(s, ARM_FEATURE_V8)) {
+ /* The Thumb2 and ARM encodings are identical. */
+ if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
+ goto illegal_op;
+ }
+ } else if (((insn >> 24) & 3) == 3) {
/* Translate into the equivalent ARM encoding. */
insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28);
if (disas_neon_data_insn(s, insn)) {
--
2.16.2
- [Qemu-devel] [PULL 34/39] target/arm: Decode aa64 armv8.3 fcadd, (continued)
- [Qemu-devel] [PULL 34/39] target/arm: Decode aa64 armv8.3 fcadd, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 39/39] target/arm: Enable ARM_FEATURE_V8_FCMA, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 29/39] target/arm: Decode aa64 armv8.1 scalar/vector x indexed element, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 23/39] mps2-an505: New board model: MPS2 with AN505 Cortex-M33 FPGA image, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 27/39] target/arm: Decode aa64 armv8.1 scalar three same extra, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 32/39] target/arm: Enable ARM_FEATURE_V8_RDM, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 31/39] target/arm: Decode aa32 armv8.1 two reg and a scalar, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 35/39] target/arm: Decode aa64 armv8.3 fcmla, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 30/39] target/arm: Decode aa32 armv8.1 three same, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 36/39] target/arm: Decode aa32 armv8.3 3-same, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 38/39] target/arm: Decode t32 simd 3reg and 2reg_scalar extension,
Peter Maydell <=
- [Qemu-devel] [PULL 37/39] target/arm: Decode aa32 armv8.3 2-reg-index, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 33/39] target/arm: Add ARM_FEATURE_V8_FCMA, Peter Maydell, 2018/03/02
- Re: [Qemu-devel] [PULL 00/39] target-arm queue, no-reply, 2018/03/02
- Re: [Qemu-devel] [PULL 00/39] target-arm queue, Peter Maydell, 2018/03/02