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Re: [Qemu-devel] [PATCH v8 23/23] RISC-V Build Infrastructure
From: |
Michael Clark |
Subject: |
Re: [Qemu-devel] [PATCH v8 23/23] RISC-V Build Infrastructure |
Date: |
Sat, 3 Mar 2018 15:37:47 +1300 |
Let me know if you have a branch for me to pull and rebase against.
We are passing all build and make check tests in travis (except for a
couple of build timeouts because we are hitting the default 50 minute
timeout)
https://travis-ci.org/riscv/riscv-qemu/builds/348234736
On Sat, Mar 3, 2018 at 3:33 AM, Eric Blake <address@hidden> wrote:
> On 03/02/2018 07:51 AM, Michael Clark wrote:
>
>> This adds RISC-V into the build system enabling the following targets:
>>
>> - riscv32-softmmu
>> - riscv64-softmmu
>> - riscv32-linux-user
>> - riscv64-linux-user
>>
>> This adds defaults configs for RISC-V, enables the build for the RISC-V
>> CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh'
>> script is updated to add the RISC-V ELF magic.
>>
>> Expected checkpatch errors for consistency reasons:
>>
>> ERROR: line over 90 characters
>> FILE: scripts/qemu-binfmt-conf.sh
>>
>> Reviewed-by: Richard Henderson <address@hidden>
>> Signed-off-by: Sagar Karandikar <address@hidden>
>> Signed-off-by: Michael Clark <address@hidden>
>> ---
>> arch_init.c | 2 ++
>> configure | 13 +++++++++++++
>> cpus.c | 6 ++++++
>> default-configs/riscv32-linux-user.mak | 1 +
>> default-configs/riscv32-softmmu.mak | 4 ++++
>> default-configs/riscv64-linux-user.mak | 1 +
>> default-configs/riscv64-softmmu.mak | 4 ++++
>> hw/riscv/Makefile.objs | 11 +++++++++++
>> include/sysemu/arch_init.h | 1 +
>> qapi-schema.json | 17 ++++++++++++++++-
>>
>
> Will need rebasing to modify qapi/misc.json if my pending PULL request
> issues get resolved first:
>
> https://lists.gnu.org/archive/html/qemu-devel/2018-03/msg00469.html
>
> --
> Eric Blake, Principal Software Engineer
> Red Hat, Inc. +1-919-301-3266
> Virtualization: qemu.org | libvirt.org
>
- Re: [Qemu-devel] [PATCH v8 19/23] SiFive RISC-V UART Device, (continued)
- Re: [Qemu-devel] [PATCH v8 19/23] SiFive RISC-V UART Device, Mark Cave-Ayland, 2018/03/10
- Re: [Qemu-devel] [PATCH v8 19/23] SiFive RISC-V UART Device, Bastian Koppelmann, 2018/03/11
- Re: [Qemu-devel] [PATCH v8 19/23] SiFive RISC-V UART Device, Michael Clark, 2018/03/16
- Re: [Qemu-devel] [PATCH v8 19/23] SiFive RISC-V UART Device, Michael Clark, 2018/03/16
- Re: [Qemu-devel] [PATCH v8 19/23] SiFive RISC-V UART Device, Bastian Koppelmann, 2018/03/16
[Qemu-devel] [PATCH v8 20/23] SiFive RISC-V PRCI Block, Michael Clark, 2018/03/02
[Qemu-devel] [PATCH v8 21/23] SiFive Freedom E Series RISC-V Machine, Michael Clark, 2018/03/02
[Qemu-devel] [PATCH v8 22/23] SiFive Freedom U Series RISC-V Machine, Michael Clark, 2018/03/02
[Qemu-devel] [PATCH v8 23/23] RISC-V Build Infrastructure, Michael Clark, 2018/03/02
Re: [Qemu-devel] [PATCH v8 23/23] RISC-V Build Infrastructure, Philippe Mathieu-Daudé, 2018/03/09
Re: [Qemu-devel] [PATCH v8 00/23] RISC-V QEMU Port Submission, no-reply, 2018/03/02
Re: [Qemu-devel] [PATCH v8 00/23] RISC-V QEMU Port Submission, Richard W.M. Jones, 2018/03/05