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Re: [Qemu-devel] [PATCH v1 18/22] RISC-V: Remove braces from satp case s
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [Qemu-devel] [PATCH v1 18/22] RISC-V: Remove braces from satp case statement with |
Date: |
Tue, 6 Mar 2018 20:09:43 -0300 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 |
On 03/06/2018 05:43 PM, Michael Clark wrote:
> Signed-off-by: Michael Clark <address@hidden>
> Signed-off-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
> ---
> target/riscv/op_helper.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index dd3e417..f79716a 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -240,7 +240,7 @@ void csr_write_helper(CPURISCVState *env, target_ulong
> val_to_write,
> csr_write_helper(env, next_mie, CSR_MIE);
> break;
> }
> - case CSR_SATP: /* CSR_SPTBR */ {
> + case CSR_SATP: /* CSR_SPTBR */
> if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
> break;
> }
> @@ -258,7 +258,6 @@ void csr_write_helper(CPURISCVState *env, target_ulong
> val_to_write,
> env->satp = val_to_write;
> }
> break;
> - }
> case CSR_SEPC:
> env->sepc = val_to_write;
> break;
>
- Re: [Qemu-devel] [PATCH v1 09/22] RISC-V: Include hexidecimal instruction in, (continued)
- [Qemu-devel] [PATCH v1 11/22] RISC-V: Improve page table walker spec compliance, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 10/22] RISC-V: Hold rcu_read_lock when accessing memory, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 12/22] RISC-V: Update E order and I extension order, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 13/22] RISC-V: Make spike and virt header guards more, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 15/22] RISC-V: Use memory_region_is_ram in atomic pte, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 14/22] RISC-V: Make virt header comment title consistent, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 16/22] RISC-V: Remove EM_RISCV ELF_MACHINE indirection from, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 18/22] RISC-V: Remove braces from satp case statement with, Michael Clark, 2018/03/06
- Re: [Qemu-devel] [PATCH v1 18/22] RISC-V: Remove braces from satp case statement with,
Philippe Mathieu-Daudé <=
- [Qemu-devel] [PATCH v1 17/22] RISC-V: Ingore satp writes and return 0 for reads, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 19/22] RISC-V: riscv-qemu port supports sv39 and sv48, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 20/22] RISC-V: vectored traps are optional, Michael Clark, 2018/03/06
- Re: [Qemu-devel] [PATCH v1 00/22] Spec conformance bug fixes and cleanups, Michael Clark, 2018/03/06