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Re: [Qemu-devel] [PATCH v2 16/23] RISC-V: Remove EM_RISCV ELF_MACHINE in
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [Qemu-devel] [PATCH v2 16/23] RISC-V: Remove EM_RISCV ELF_MACHINE indirection |
Date: |
Sat, 10 Mar 2018 21:32:10 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 |
On 03/09/2018 05:12 AM, Michael Clark wrote:
> Pointless indirection. Other ports use EM_ constants directly.
>
> Cc: Sagar Karandikar <address@hidden>
> Cc: Bastian Koppelmann <address@hidden>
> Signed-off-by: Michael Clark <address@hidden>
> Signed-off-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
> ---
> hw/riscv/sifive_e.c | 2 +-
> hw/riscv/sifive_u.c | 2 +-
> hw/riscv/spike.c | 2 +-
> hw/riscv/virt.c | 2 +-
> target/riscv/cpu.h | 1 -
> 5 files changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 4872b68..39e4cb4 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -88,7 +88,7 @@ static uint64_t load_kernel(const char *kernel_filename)
>
> if (load_elf(kernel_filename, NULL, NULL,
> &kernel_entry, NULL, &kernel_high,
> - 0, ELF_MACHINE, 1, 0) < 0) {
> + 0, EM_RISCV, 1, 0) < 0) {
> error_report("qemu: could not load kernel '%s'", kernel_filename);
> exit(1);
> }
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 57b4f4f..0e633a0 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -74,7 +74,7 @@ static uint64_t load_kernel(const char *kernel_filename)
>
> if (load_elf(kernel_filename, NULL, NULL,
> &kernel_entry, NULL, &kernel_high,
> - 0, ELF_MACHINE, 1, 0) < 0) {
> + 0, EM_RISCV, 1, 0) < 0) {
> error_report("qemu: could not load kernel '%s'", kernel_filename);
> exit(1);
> }
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index c7d937b..70e697c 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -64,7 +64,7 @@ static uint64_t load_kernel(const char *kernel_filename)
> uint64_t kernel_entry, kernel_high;
>
> if (load_elf_ram_sym(kernel_filename, NULL, NULL,
> - &kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0,
> + &kernel_entry, NULL, &kernel_high, 0, EM_RISCV, 1, 0,
> NULL, true, htif_symbol_callback) < 0) {
> error_report("qemu: could not load kernel '%s'", kernel_filename);
> exit(1);
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index d680cbd..e3f8bb7 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -68,7 +68,7 @@ static uint64_t load_kernel(const char *kernel_filename)
>
> if (load_elf(kernel_filename, NULL, NULL,
> &kernel_entry, NULL, &kernel_high,
> - 0, ELF_MACHINE, 1, 0) < 0) {
> + 0, EM_RISCV, 1, 0) < 0) {
> error_report("qemu: could not load kernel '%s'", kernel_filename);
> exit(1);
> }
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 3a0ca2f..7c4482b 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -34,7 +34,6 @@
>
> #define TCG_GUEST_DEFAULT_MO 0
>
> -#define ELF_MACHINE EM_RISCV
> #define CPUArchState struct CPURISCVState
>
> #include "qemu-common.h"
>
- [Qemu-devel] [PATCH v2 09/23] RISC-V: Include intruction hex in disassembly, (continued)
- [Qemu-devel] [PATCH v2 09/23] RISC-V: Include intruction hex in disassembly, Michael Clark, 2018/03/08
- [Qemu-devel] [PATCH v2 10/23] RISC-V: Hold rcu_read_lock when accessing memory, Michael Clark, 2018/03/08
- [Qemu-devel] [PATCH v2 11/23] RISC-V: Improve page table walker spec compliance, Michael Clark, 2018/03/08
- [Qemu-devel] [PATCH v2 12/23] RISC-V: Update E order and I extension order, Michael Clark, 2018/03/08
- [Qemu-devel] [PATCH v2 14/23] RISC-V: Make virt header comment title consistent, Michael Clark, 2018/03/08
- [Qemu-devel] [PATCH v2 13/23] RISC-V: Make some header guards more specific, Michael Clark, 2018/03/08
- [Qemu-devel] [PATCH v2 16/23] RISC-V: Remove EM_RISCV ELF_MACHINE indirection, Michael Clark, 2018/03/08
- Re: [Qemu-devel] [PATCH v2 16/23] RISC-V: Remove EM_RISCV ELF_MACHINE indirection,
Philippe Mathieu-Daudé <=
- [Qemu-devel] [PATCH v2 15/23] RISC-V: Use memory_region_is_ram in pte update, Michael Clark, 2018/03/08
- [Qemu-devel] [PATCH v2 17/23] RISC-V: Hardwire satp to 0 for no-mmu case, Michael Clark, 2018/03/08
- [Qemu-devel] [PATCH v2 18/23] RISC-V: Remove braces from satp case statement, Michael Clark, 2018/03/08
- [Qemu-devel] [PATCH v2 19/23] RISC-V: riscv-qemu port supports sv39 and sv48, Michael Clark, 2018/03/08
- [Qemu-devel] [PATCH v2 20/23] RISC-V: vectored traps are optional, Michael Clark, 2018/03/08
- [Qemu-devel] [PATCH v2 21/23] RISC-V: No traps on writes to misa, minstret, mcycle, Michael Clark, 2018/03/08
- [Qemu-devel] [PATCH v2 22/23] RISC-V: Remove support for adhoc X_COP interrupt, Michael Clark, 2018/03/08
- [Qemu-devel] [PATCH v2 23/23] RISC-V: Convert cpu definition towards future model, Michael Clark, 2018/03/08