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Re: [Qemu-devel] Using new TCG Vector infrastructure in PowerPC


From: Nikunj A Dadhania
Subject: Re: [Qemu-devel] Using new TCG Vector infrastructure in PowerPC
Date: Fri, 16 Mar 2018 09:38:14 +0530

Richard Henderson <address@hidden> writes:

> On 03/07/2018 06:03 PM, Nikunj A Dadhania wrote:
>> Hi Richard,
>> 
>> I was working to get TCG vector support for PowerPC[1]. Started with
>> converting logical operations like vector AND/OR/XOR and compare
>> instructions. Found some inconsistency during my testing on x86 laptop
>> emulating PowerPC:
>
> Great.
>
> Well, the problem is that you cannot use TCG generic vectors and TCG global
> variables to access the same memory.

Interesting, wasn't aware of this.

> Thus your first step must be to remove all references to cpu_avrh and 
> cpu_avrl.
>  These can be replaced by translator helpers that perform an explicit
> tcg_gen_ld_i64 or tcg_gen_st_i64 to the proper memory locations.
>
> Only after that's done can you begin converting other references to use the
> host vectors.  Otherwise, the tcg optimizer will do Bad and Unpredictable
> Things, which may well have produced the incorrect results that you saw.
>
> I'll note that it's probably worth rearranging all of {fpr,vsr,avr} to the 
> more
> logical configuration presented by Power7 (?) such that it's one array of 64 x
> 128-bit registers.

I have following for taking care of making VSRs contiguous 128bits. This
has touched lot of code even out of tcg directory. So I currently have
32 AVRs (128bits) and 32 VSRs (128 bits).

@@ -1026,8 +1027,8 @@ struct CPUPPCState {
 
     /* Floating point execution context */
     float_status fp_status;
-    /* floating point registers */
-    float64 fpr[32];
+    /* floating point registers multiplexed with vsr */
+
     /* floating point status and control register */
     target_ulong fpscr;
 
@@ -1078,8 +1079,8 @@ struct CPUPPCState {
     /* Altivec registers */
     ppc_avr_t avr[32];
     uint32_t vscr;
-    /* VSX registers */
-    uint64_t vsr[32];
+    /* 32 (128bit)- VSX registers */
+    ppc_avr_t vsr[32];
     /* SPE registers */
     uint64_t spe_acc;
     uint32_t spe_fscr;

Regards,
Nikunj




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