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[Qemu-devel] [PATCH v3 16/22] target/arm: Implement PMOVSSET
From: |
Aaron Lindsay |
Subject: |
[Qemu-devel] [PATCH v3 16/22] target/arm: Implement PMOVSSET |
Date: |
Fri, 16 Mar 2018 16:31:14 -0400 |
Adding an array for v7VE+ CP registers was necessary so that PMOVSSET
wasn't defined for all v7 processors.
Signed-off-by: Aaron Lindsay <address@hidden>
---
target/arm/helper.c | 32 +++++++++++++++++++++++++++++++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d4f06e6..f5e800e 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1241,9 +1241,17 @@ static void pmcntenclr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
+ value &= PMU_COUNTER_MASK(env);
env->cp15.c9_pmovsr &= ~value;
}
+static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ value &= PMU_COUNTER_MASK(env);
+ env->cp15.c9_pmovsr |= value;
+}
+
static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -1406,7 +1414,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
.writefn = pmcntenclr_write },
{ .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
- .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
+ .access = PL0_RW, .fieldoffset = offsetoflow32(CPUARMState,
cp15.c9_pmovsr),
.accessfn = pmreg_access,
.writefn = pmovsr_write,
.raw_writefn = raw_write },
@@ -1592,6 +1600,25 @@ static const ARMCPRegInfo v7mp_cp_reginfo[] = {
REGINFO_SENTINEL
};
+static const ARMCPRegInfo v7ve_cp_reginfo[] = {
+ /* Performance monitor registers which are not implemented in v7 before
+ * v7ve:
+ */
+ { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3,
+ .access = PL0_RW, .accessfn = pmreg_access,
+ .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
+ .writefn = pmovsset_write,
+ .raw_writefn = raw_write },
+ { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3,
+ .access = PL0_RW, .accessfn = pmreg_access,
+ .type = ARM_CP_ALIAS,
+ .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
+ .writefn = pmovsset_write,
+ .raw_writefn = raw_write },
+ REGINFO_SENTINEL
+};
+
static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -4943,6 +4970,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
!arm_feature(env, ARM_FEATURE_PMSA)) {
define_arm_cp_regs(cpu, v7mp_cp_reginfo);
}
+ if (arm_feature(env, ARM_FEATURE_V7VE)) {
+ define_arm_cp_regs(cpu, v7ve_cp_reginfo);
+ }
if (arm_feature(env, ARM_FEATURE_V7)) {
/* v7 performance monitor control register: same implementor
* field as main ID register, and we implement only the cycle
--
Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
- [Qemu-devel] [PATCH v3 12/22] target/arm: Filter cycle counter based on PMCCFILTR_EL0, (continued)
- [Qemu-devel] [PATCH v3 12/22] target/arm: Filter cycle counter based on PMCCFILTR_EL0, Aaron Lindsay, 2018/03/16
- [Qemu-devel] [PATCH v3 11/22] target/arm: Fix bitmask for PMCCFILTR writes, Aaron Lindsay, 2018/03/16
- [Qemu-devel] [PATCH v3 15/22] target/arm: Add ARM_FEATURE_V7VE for v7 Virtualization Extensions, Aaron Lindsay, 2018/03/16
- [Qemu-devel] [PATCH v3 18/22] target/arm: Add array for supported PMU events, generate PMCEID[01], Aaron Lindsay, 2018/03/16
- [Qemu-devel] [PATCH v3 17/22] target/arm: Split arm_ccnt_enabled into generic pmu_counter_enabled, Aaron Lindsay, 2018/03/16
- [Qemu-devel] [PATCH v3 20/22] target/arm: PMU: Add instruction and cycle events, Aaron Lindsay, 2018/03/16
- [Qemu-devel] [PATCH v3 16/22] target/arm: Implement PMOVSSET,
Aaron Lindsay <=
- [Qemu-devel] [PATCH v3 21/22] target/arm: PMU: Set PMCR.N to 4, Aaron Lindsay, 2018/03/16
- [Qemu-devel] [PATCH v3 22/22] target/arm: Implement PMSWINC, Aaron Lindsay, 2018/03/16
- [Qemu-devel] [PATCH v3 19/22] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER, Aaron Lindsay, 2018/03/16
- Re: [Qemu-devel] [PATCH v3 00/22] More fully implement ARM PMUv3, no-reply, 2018/03/16