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[Qemu-devel] [PULL 17/24] RISC-V: Remove braces from satp case statement
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PULL 17/24] RISC-V: Remove braces from satp case statement |
Date: |
Wed, 21 Mar 2018 13:46:53 -0700 |
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
---
target/riscv/op_helper.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index dd3e417..f79716a 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -240,7 +240,7 @@ void csr_write_helper(CPURISCVState *env, target_ulong
val_to_write,
csr_write_helper(env, next_mie, CSR_MIE);
break;
}
- case CSR_SATP: /* CSR_SPTBR */ {
+ case CSR_SATP: /* CSR_SPTBR */
if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
break;
}
@@ -258,7 +258,6 @@ void csr_write_helper(CPURISCVState *env, target_ulong
val_to_write,
env->satp = val_to_write;
}
break;
- }
case CSR_SEPC:
env->sepc = val_to_write;
break;
--
2.7.0
- [Qemu-devel] [PULL 00/24] RISC-V: Post-merge spec conformance and cleanup v5, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 04/24] RISC-V: Use ROM base address and size from memmap, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 01/24] RISC-V: Make virt create_fdt interface consistent, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 03/24] RISC-V: Make virt board description match spike, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 02/24] RISC-V: Replace hardcoded constants with enum values, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 07/24] RISC-V: Remove unused class definitions, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 06/24] RISC-V: Mark ROM read-only after copying in code, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 05/24] RISC-V: Remove identity_translate from load_elf, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 14/24] RISC-V: Use memory_region_is_ram in pte update, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 11/24] RISC-V: Update E order and I extension order, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 17/24] RISC-V: Remove braces from satp case statement,
Michael Clark <=
- [Qemu-devel] [PULL 18/24] RISC-V: riscv-qemu port supports sv39 and sv48, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 20/24] RISC-V: No traps on writes to misa, minstret, mcycle, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 19/24] RISC-V: vectored traps are optional, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 09/24] RISC-V: Include intruction hex in disassembly, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 08/24] RISC-V: Make sure rom has space for fdt, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 10/24] RISC-V: Improve page table walker spec compliance, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 13/24] RISC-V: Make virt header comment title consistent, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 12/24] RISC-V: Make some header guards more specific, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 15/24] RISC-V: Remove EM_RISCV ELF_MACHINE indirection, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 23/24] RISC-V: Clear mtval/stval on exceptions without info, Michael Clark, 2018/03/21